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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9c20616sm127945975ad.34.2026.07.14.23.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:23:14 -0700 (PDT) From: Qiang Yu Date: Tue, 14 Jul 2026 23:23:13 -0700 Subject: [PATCH] clk: qcom: gcc: Set FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON for PCIe pipe clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-mem_on-v1-1-f5bfb6def0a1@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAFAnV2oC/2WNQQ6CMBBFr0JmbUmLWMWV9zDElDpIjaXagUZDe ndbXLqZ5CXvv1mA0BskOBYLeAyGjBsTiE0BelDjDZm5JoaKV5LvecMs2osbGdd13/Atl7qTkOS nx96819C5/THN3R31lNfZGAxNzn/WT0Fk7y8aBBOsU6ms651s8HByROVrVg/trC3TgTbG+AWWi rb2tQAAAA== X-Change-ID: 20260709-mem_on-0c4f90306cb6 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784096594; l=4719; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=80rMppBxr7aVVbSmG1tEhmzZwzZslaQo+qJjlFgRLIQ=; b=lwvHAVWpFZNleTYEwBZPeo8+HkfjBkDkboPGZC3KelhDFg+pCsG6aN1bz/Ww8wIYtgA2haHXd voAXStQU45xDBo8Kd2CEQsrOgGjDhM48JQaBc++j+e71BC+qzkPfB2J X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: 6v53qbqt4sfmPSZvYhywPx9xyyby2_IU X-Authority-Analysis: v=2.4 cv=E+v9Y6dl c=1 sm=1 tr=0 ts=6a572754 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=Zdl20m3D5pEWJIyXYvkA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDA1OSBTYWx0ZWRfX5m3g4ko04Atj 5b7y4PFCzm/5lhT2NZ5pR2tyAF4X5/kY+f6k3kZgnH84pgbQlirYibvy6/+0K4/+YEvHwktVGJN ItOxYLTj5w0OciwX509szDjv2AYRSz0HdHFlY0v6buDUPBW2f9co7r+htBng4gAaPwe6lWRsR8n 0Vzpj7Jjcs4pPAoGwmNO+7n5ywS1UaRsyURpZ/D+DtBgG8goHOhjBZnnB+1aNW+vLF/teo8rbrH TL84TB7ippF74R2onkWp5RDXyABhpzo5xG1H4F0ug50oXtU32XtownHNEqULN5AHFhpjqa53+uV iLxxF59rIgn/ZxA3F7FDQ7YbPuSOVRPERosVBjtJ5Dbs+HmDpp87ctArkEdNhsNXZtxHB7yHwb8 wYbDIv2Z5Ulrh8wmVdLxWIdpHDQdSxk1bSb1G/ZMA+g3rdZ3Quktnh11PdlWz2VfQaaM3siWjy4 aNW+HzINBG7/1mrgDRg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDA1OSBTYWx0ZWRfX1xWfxKLZ+r2q pNTx0DXBAiwmtaoDQrzQXOAiVA5ytP56MGaL2v4LWW6gPMkxHQx+f3ewxIx/61YVqj6md21Yqm8 WqQ0+T7/ouwoSloAxRz3SQW4G0C+dqg= X-Proofpoint-GUID: 6v53qbqt4sfmPSZvYhywPx9xyyby2_IU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150059 Setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON for the PCIe PIPE clocks so that the inbound data path works correctly. Without this, the PCIe link can come up but the endpoint can not access host memory, with the host sometimes seeing a completion timeout reported by the EP, even though the host can still read the EP's config space. This issue is seen on QDU1000, Kaanapali, Glymur and Nord. Hence, apply FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on these platforms. Signed-off-by: Qiang Yu --- drivers/clk/qcom/gcc-glymur.c | 11 +++++++++++ drivers/clk/qcom/gcc-kaanapali.c | 3 +++ drivers/clk/qcom/gcc-nord.c | 13 +++++++++++++ drivers/clk/qcom/gcc-qdu1000.c | 3 +++ 4 files changed, 30 insertions(+) diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c index 6925c6865089..1e33160e03fb 100644 --- a/drivers/clk/qcom/gcc-glymur.c +++ b/drivers/clk/qcom/gcc-glymur.c @@ -8530,6 +8530,17 @@ static void clk_glymur_regs_configure(struct device = *dev, struct regmap *regmap) { /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + + qcom_branch_set_force_mem_core(regmap, gcc_pcie_3a_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_3a_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_3b_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_3b_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_4_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_4_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_5_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_5_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_6_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_6_pipe_clk, true); } =20 static const struct qcom_cc_driver_data gcc_glymur_driver_data =3D { diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanap= ali.c index 842c1a70c691..4bde2dcfc4fb 100644 --- a/drivers/clk/qcom/gcc-kaanapali.c +++ b/drivers/clk/qcom/gcc-kaanapali.c @@ -3482,6 +3482,9 @@ static void clk_kaanapali_regs_configure(struct devic= e *dev, struct regmap *regm { /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + + qcom_branch_set_force_mem_core(regmap, gcc_pcie_0_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_0_pipe_clk, true); } =20 static const struct qcom_cc_driver_data gcc_kaanapali_driver_data =3D { diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c index 7c7c2171ac96..66889e9159ec 100644 --- a/drivers/clk/qcom/gcc-nord.c +++ b/drivers/clk/qcom/gcc-nord.c @@ -1849,9 +1849,22 @@ static const struct regmap_config gcc_nord_regmap_co= nfig =3D { .fast_io =3D true, }; =20 +static void clk_nord_regs_configure(struct device *dev, struct regmap *reg= map) +{ + qcom_branch_set_force_mem_core(regmap, gcc_pcie_a_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_a_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_b_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_b_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_c_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_c_pipe_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_pcie_d_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_d_pipe_clk, true); +} + static const struct qcom_cc_driver_data gcc_nord_driver_data =3D { .dfs_rcgs =3D gcc_nord_dfs_clocks, .num_dfs_rcgs =3D ARRAY_SIZE(gcc_nord_dfs_clocks), + .clk_regs_configure =3D clk_nord_regs_configure, }; =20 static const struct qcom_cc_desc gcc_nord_desc =3D { diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 915bb9b4ff81..18ed351f2a16 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -2669,6 +2669,9 @@ static int gcc_qdu1000_probe(struct platform_device *= pdev) /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */ regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); =20 + qcom_branch_set_force_mem_core(regmap, gcc_pcie_0_pipe_clk, true); + qcom_branch_set_force_periph_on(regmap, gcc_pcie_0_pipe_clk, true); + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) --- base-commit: b9810cd75b9fb56a3425d391cba3f608502bd474 change-id: 20260709-mem_on-0c4f90306cb6 Best regards, -- =20 Qiang Yu