[v2] clocksource/timer-econet-en751221: Support irq number per timer

[PATCH v2 0/5] clocksource/timer-econet-en751221: Support irq number per timer

Caleb James DeLisle posted 5 patches 4 weeks, 1 day ago

Diff against v1 v3 v4 v5 v6
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.../bindings/timer/econet,en751221-timer.yaml |  16 ++-
drivers/clocksource/timer-econet-en751221.c   | 123 +++++++++++++++---
2 files changed, 117 insertions(+), 22 deletions(-)

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[PATCH v2 0/5] clocksource/timer-econet-en751221: Support irq number per timer

Posted by Caleb James DeLisle 4 weeks, 1 day ago

In prep for adding EN751627 and EN7528 SoCs, we need to support the GIC
interrupt controller. Unlike the intc in the EN751221, this intc does
not create a percpu interrupt for the timers, so we update the timer
driver to support both models.

Changes from v1:
* Split changes over 3 refactoring patches + main patch
* Remove driver discussion from dt commit message
* v1: https://lore.kernel.org/linux-mips/20260416175101.958073-1-cjd@cjdns.fr/

Caleb James DeLisle (5):
  dt-bindings: timer: econet: Update EN751627 for multi-IRQ
  clocksource/timer-econet-en751221: Move generic logic out of cevt_init
  clocksource/timer-econet-en751221: Always map all membase blocks
  clocksource/timer-econet-en751221: Unmap io mem on probe error
  clocksource/timer-econet-en751221: Support irq number per timer

 .../bindings/timer/econet,en751221-timer.yaml |  16 ++-
 drivers/clocksource/timer-econet-en751221.c   | 123 +++++++++++++++---
 2 files changed, 117 insertions(+), 22 deletions(-)


base-commit: ff1c0c5d07028a84837950b619d30da623f8ddb2
-- 
2.39.5