From nobody Fri Jun 12 15:58:07 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E21276025; Thu, 14 May 2026 00:06:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717178; cv=none; b=R+UU8YOHU0/+ODIPkKHW+BGEWE1bT3bEetgVg5pnZoRvAymim0eR0i1wIK6hckbDEJAhWe4/yfT3uxNuLWaKiDZdJhWIPuKs0XJflDbSWI5cY5d7dcicN0TFuZDoE4mzGiq3YoZ4IFC+8+9AnPaGy6tFWNXdGIrzLRd6u0YJpBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717178; c=relaxed/simple; bh=FgG58eGhmlC/n7pbzl1OSAbZ0nk5KWnJCNVx2x8GEj8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=M7X63hcm7GD6QA33UOzwIchosjghb2Hb35VWO8mVId2h0dyori75JsPcGbepCxUXkj1vmwOLlAl+Jrow9Br1MyMUDuDpTePj6uAbvnWm+7k31pMj5qqpjagIoRv+fgLchs7LXP1/U+mMPACShkRQyWoBk+2eo01osC5do0CJFow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=T0VLhdAp; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="T0VLhdAp" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B5D543CC101; Thu, 14 May 2026 02:06:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778717174; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=wXacb0n2TMynhlrS3dc3M2K/Xjj68GSTktVtpr2SWrY=; b=T0VLhdApP8X6xpIuM1owehSkVwOwKIUwk9jBnaC5WW7mhTBU43M0PIsEzKTAN+8+0qbyNe 00D7iF9Tvsn/p4AZ02+R5zaVZDgP8l2bSWWloInysHNGLfqP3QbrkHBUQ9LaPWQ5zBxr1h 0VspTuTAtOtjAjCRW6Dz5AFfblZ00fATPe0/HcT2GNiRvTRe9Xjs995aMmyqcANYkg5qyJ rvcVL+a38S72G/6DIuZ8tBNDfvUnPBqUUroHN5ONcCRyxd+JBkiBPZltUNtG21natr+phO 25G4oYmR6oOjjFtCakvLDTHRUnnl03fTHsqK72dwd/q4cnRInM1wHkgq2iP5Qw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle , Conor Dooley Subject: [PATCH v2 1/5] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Date: Thu, 14 May 2026 00:05:57 +0000 Message-Id: <20260514000601.3430262-2-cjd@cjdns.fr> In-Reply-To: <20260514000601.3430262-1-cjd@cjdns.fr> References: <20260514000601.3430262-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This hardware is found in the EN751221 SoC family as well as the EN751627. The former uses a percpu IRQ for all timers while the later uses an individual IRQ numbers per-timer. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/timer/econet,en751221-timer.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.= yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml index c1e7c2b6afde..f338739e039c 100644 --- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -28,8 +28,8 @@ properties: maxItems: 2 =20 interrupts: - maxItems: 1 - description: A percpu-devid timer interrupt shared across CPUs. + minItems: 1 + maxItems: 4 =20 clocks: maxItems: 1 @@ -52,21 +52,31 @@ allOf: items: - description: VPE timers 0 and 1 - description: VPE timers 2 and 3 + interrupts: + description: An interrupt for each timer (one per VPE) + minItems: 4 else: properties: reg: items: - description: VPE timers 0 and 1 + interrupts: + description: A percpu-devid timer interrupt shared across timers + maxItems: 1 =20 additionalProperties: false =20 examples: - | + #include timer@1fbf0400 { compatible =3D "econet,en751627-timer", "econet,en751221-timer"; reg =3D <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; interrupt-parent =3D <&intc>; - interrupts =3D <30>; + interrupts =3D , + , + , + ; clocks =3D <&hpt_clock>; }; - | --=20 2.39.5 From nobody Fri Jun 12 15:58:07 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A435198A17; Thu, 14 May 2026 00:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717181; cv=none; b=Bpry0C1SeElZ+RVuRey1C9ro19JdhgRIPzcLG/nuDzl3dN2rkdtFTDuq3FSnjMGWrsGhqrYJHhPZ4Du8Gup19UMKwOiYdFuU1v965u32DZI5cpVQ9CF4W8TD9lyhitBWUQws7qJYfh6Vbhx9W7QbKmsPE1yB2C/xQNdtwXVvXPM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717181; c=relaxed/simple; bh=oZNBhEbHSvwxysGd4ekKEToBKkq9YVk15RpEEgR1s7Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pD35BPOgJ1hO9KcwQh1a6OUYIDVF2uznv4rzUpNoGxFaXBg4WQgX8/Ie1efQbS5vAUNb0Leak3qLbm95pCRxZQVS+hJyNTtAgTdik3lEtqSwQovsJAhvhBSu9prVGsqTGYyvSUOaFkGatIoLb9ryOAbOsRiN6yYP9rnPAgOY6/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=feRVeWam; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="feRVeWam" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CBF273CAB62; Thu, 14 May 2026 02:06:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778717176; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=r5PfJvgee09PC78soNW2xInK8l/vzvC6AIBcmRiE2E8=; b=feRVeWamZvF5bqsiVDNeVM3WoKz9S9c/BSQvIWOO9hWVNjgC1nmLQxtdHY8+tc6KDQAfuk GOmju/9WEzvxmB8NpRWXhi+/ZYKaj2CA6dXB1h7kJRhZUV16TMp3YrV6ZDW6S3K5nIo/dL UsdhAZE53flDoYTiSjMkEB3yeMDvezrhuWfBef4XmutMIHARvoHCj3tzmnAR5fqZU5KxK8 JfUJ7hHtSqRv5jYvKRj+FxgGiTS05fwdEgV4MBGzqQGzpQxKGOxBN0LY4YVFan5As9egKg rewWyL8atzkQLME7waIhyKkBQZNmas1nufVMBUodzFLOjGo31IN61re1W1BIFg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v2 2/5] clocksource/timer-econet-en751221: Move generic logic out of cevt_init Date: Thu, 14 May 2026 00:05:58 +0000 Message-Id: <20260514000601.3430262-3-cjd@cjdns.fr> In-Reply-To: <20260514000601.3430262-1-cjd@cjdns.fr> References: <20260514000601.3430262-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In preparation for supporting either a percpu IRQ or multiple IRQ numbers, simplify cevt_init with common code moved out. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 31 +++++++++++++-------- 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 4008076b1a21..5def3e536b21 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -126,6 +126,19 @@ static void __init cevt_dev_init(uint cpu) iowrite32(U32_MAX, reg_compare(cpu)); } =20 +static void __init cevt_setup_clockevent(struct clock_event_device *cd, + struct device_node *np, + int irq, int cpu) +{ + cd->rating =3D 310; + cd->features =3D CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_C3STOP; + cd->set_next_event =3D cevt_set_next_event; + cd->irq =3D irq; + cd->cpumask =3D cpumask_of(cpu); + cd->name =3D np->name; +} + static int __init cevt_init(struct device_node *np) { int i, irq, ret; @@ -146,21 +159,11 @@ static int __init cevt_init(struct device_node *np) for_each_possible_cpu(i) { struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, i); =20 - cd->rating =3D 310; - cd->features =3D CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_C3STOP | - CLOCK_EVT_FEAT_PERCPU; - cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D irq; - cd->cpumask =3D cpumask_of(i); - cd->name =3D np->name; - + cevt_setup_clockevent(cd, np, irq, i); + cd->features |=3D CLOCK_EVT_FEAT_PERCPU; cevt_dev_init(i); } =20 - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, - "clockevents/econet/timer:starting", - cevt_init_cpu, NULL); return 0; =20 err_unmap_irq: @@ -203,6 +206,10 @@ static int __init timer_init(struct device_node *np) if (ret < 0) return ret; =20 + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "clockevents/econet/timer:starting", + cevt_init_cpu, NULL); + sched_clock_register(sched_clock_read, ECONET_BITS, econet_timer.freq_hz); =20 --=20 2.39.5 From nobody Fri Jun 12 15:58:07 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E016214A62B; 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arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Xloo44Gv" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id ADE353CAB7E; Thu, 14 May 2026 02:06:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778717180; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=TG1hR2+yRACPSEJR+pfdcc8iUip3vVJTgeUnuo2wD7Y=; b=Xloo44GvvB1Pm9TMvqRlaYCZ2f1rtbpEDylB4/sYB/noKHv7xb8kG9/QcOkc0xKVMm0xHI sMzX47M9aWoTuYgLIh7Eu30OwdK/A+0QiR9GHKYjhEWzDVnRTXZ2XzO8ZuTqoiY9FG2z1K Ef9NzSFNtWPL4yAllkKmy5BWADH8jOlWSdmVN6YSeRNSKf/g1xGkX7lyE7w97GUkIqM23n enjC7jlYD7OP25/Jx0XGfZbUXZgKc01189h5wzeGMh/OOoYa/XiDAniYY6sXbEwwZpBbp1 1XNTskK84r21VvuROYLgKSb3r1xHZt6nqecS7YvtPvVO/f524tB+7Hzx2GqDsg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v2 3/5] clocksource/timer-econet-en751221: Always map all membase blocks Date: Thu, 14 May 2026 00:05:59 +0000 Message-Id: <20260514000601.3430262-4-cjd@cjdns.fr> In-Reply-To: <20260514000601.3430262-1-cjd@cjdns.fr> References: <20260514000601.3430262-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The 34Kc always has 1 block and the 1004Kc always has 2, there's no reason to not map them all, even if some CPUs are not active. Simplify the logic to make it more maintainable. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 5def3e536b21..e79069d9a826 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -173,7 +173,6 @@ static int __init cevt_init(struct device_node *np) =20 static int __init timer_init(struct device_node *np) { - int num_blocks =3D DIV_ROUND_UP(num_possible_cpus(), 2); struct clk *clk; int ret; =20 @@ -185,7 +184,7 @@ static int __init timer_init(struct device_node *np) =20 econet_timer.freq_hz =3D clk_get_rate(clk); =20 - for (int i =3D 0; i < num_blocks; i++) { + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); --=20 2.39.5 From nobody Fri Jun 12 15:58:07 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61B1E1DB54C; Thu, 14 May 2026 00:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717187; cv=none; b=FClbGB1swI54WwFRDLXVC2znlIHyhOrqouNlVZKBlNqRgFq4A/C0bSg5KnHXeciksaC6XfkAyBLld6b1/7ABwbb2o+DWrv9+yABdxBj6H9RO7yuG/5Ms6BUUM1OqQn44dKrtiVLkHsgIXyCiOgxabOcgXMXwlHSzxpkrh7jx2Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717187; c=relaxed/simple; bh=JY/9j43Kc1bhFxarcxOb4L1EYCGR3nA3bFC7iXEP22c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q50YnDe1LsbBJ0NiTtDbjCExxDlXoqbyh3iXJfnjs7//SfeWNhbLqYTJt4MdES4s/BQOf6d3MYHxvPWrYr9iTFG2x9BqnBbC2KjNgMJv2ZRO6yF7aDweBKEwFQbhzLLzVlX4KEz65e8467nzlK1ZJXEM3qHCt5Gl9AOTjACSInk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=c6+z3sdz; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="c6+z3sdz" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 98A2C3CC215; Thu, 14 May 2026 02:06:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778717183; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=nHs+ZG7Xyt4eumxbVK7vTkSw0rUysE85PTRgQqMszug=; b=c6+z3sdzHyXk1pNy0iL3Fd29XaXYftjP3N8CQ0kf0s2G7JIBfY4Ob13DhERYkpDNzfK393 0j847VoMVwBQxHGP9ziBFxoN6o5CbVlaHUPmG0bhFDiYom5vZ3Y9iDxcd8hBf/ctQCAGRu IrVBS9qemUJp7cYtlWlZ516dnl9dMSw94wgkmH0D22sXqySjH3Kj5DsOrQPNT68fq5CTfX VGkzwQUIJRrYKDHxheFp2eixZGVN3yGlN1f4/mk74bDura34xY9r4GJTvtPzeZ1fg1Cux+ vhL1ABHpgN0R/XUqrGAwIrGqtCnAc8Yu1zIqltwkj1QUPaFICXqtaWbrPYdoKg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v2 4/5] clocksource/timer-econet-en751221: Unmap io mem on probe error Date: Thu, 14 May 2026 00:06:00 +0000 Message-Id: <20260514000601.3430262-5-cjd@cjdns.fr> In-Reply-To: <20260514000601.3430262-1-cjd@cjdns.fr> References: <20260514000601.3430262-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In case of error during probe, the io mem blocks should be unmapped. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index e79069d9a826..4b712eb4db6f 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -188,7 +188,8 @@ static int __init timer_init(struct device_node *np) econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); - return -ENXIO; + ret =3D -ENXIO; + goto err_unmap; } } =20 @@ -198,12 +199,12 @@ static int __init timer_init(struct device_node *np) clocksource_mmio_readl_up); if (ret) { pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret); - return ret; + goto err_unmap; } =20 ret =3D cevt_init(np); if (ret < 0) - return ret; + goto err_unmap; =20 cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "clockevents/econet/timer:starting", @@ -217,6 +218,14 @@ static int __init timer_init(struct device_node *np) (econet_timer.freq_hz / 1000) % 1000); =20 return 0; + +err_unmap: + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + if (econet_timer.membase[i]) + iounmap(econet_timer.membase[i]); + } + + return ret; } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); --=20 2.39.5 From nobody Fri Jun 12 15:58:07 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 615961DF748; Thu, 14 May 2026 00:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717191; cv=none; b=iI813x3g2SNjJdXpRc5A5EBdbFHtXK7l+dW8hYl1mmcq+fCLG8+M/iBGHfd801NhHohjBCBbD+qqPBefKtxNAz1AHN2wY9gfSrBXECG5PQ8olxQ1DMXpUtj7+zVSliev7SZjeWmGAc7z20qc8hdQvgKizN0C1B75VB2IyhqEpMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778717191; c=relaxed/simple; bh=IpvTnlv0vFLKt2rkVYk/KQJMPZEDq9+iMpQlGSRKVB4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jI+pfC5O2GZ2hceqTcfh8Me8egPMPhxjl33csiMiyFD4jaEJLGcegRgUAhIxEG9cBT3WEn6PDf5qzowyjt1Zv6n8qLP9VpFrfxTbzCte9EItYKYfbWAx+wwcCw4VRcLuiLZojfD5EyDL1gKPrprdlGFo1n43uvx1WTjcEwGfzMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=sXM5Kd8N; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="sXM5Kd8N" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8CBED3CAEC9; Thu, 14 May 2026 02:06:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1778717186; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=q9mlP5LpbiwbXoJmKa6RlqBhsUePdNJjaIJGAtp2bJQ=; b=sXM5Kd8N/fmEsBD/pQEmKPYBz3udisYfmch/OGbcAHfWJvWDBVhzpYYR5tjjQFGSAjP8Xg 6f/MKFrKCNw1qFvA9naLkHuEKGPlK1xAVvfl9yUpCpzOJNcOJ3qB7rKSspqqI6L8L0tzBk qvj87yyPX0IXbJlKis/cKEHpCj/spJ6ImXn9axKQVT3nNJ632rbj20H2M0xq7SSKbtiSIg S76HOjk8KPIyVfkcDmzXnWddTTsmDQAUB9GFcBLS1LXhv3pTePFCRTc/Yq6qipiHxx+tYv L6wr73iISHY3j+WsRRAMRf0JFd2zEiwyKLq+juyFHbejud0xlhMTBNvwPl5jYw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, Caleb James DeLisle Subject: [PATCH v2 5/5] clocksource/timer-econet-en751221: Support irq number per timer Date: Thu, 14 May 2026 00:06:01 +0000 Message-Id: <20260514000601.3430262-6-cjd@cjdns.fr> In-Reply-To: <20260514000601.3430262-1-cjd@cjdns.fr> References: <20260514000601.3430262-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This timer was first developed on the EN751221 which is a MIPS 34Kc and has a custom interrupt controller. The hardware for econet,en751221-intc implements percpu routing of the timer interrupts. However, the EN751627 and EN7528 are MIPS 1004Kc based, and use the standard mti,gic compatible interrupt controller. This interrupt controller uses a different IRQ number for each timer interrupt. Support both interrupt modes, percpu and individual IRQ per timer. This is based on work by Ahmed Naseef but has been refactored and broken up since then. Originally-by: Ahmed Naseef Link: https://github.com/openwrt/openwrt/commit/fab098cb6121647ca9cc6e501d5= 6ebe8a9ea550b#diff-a09ee5e4166e89df337d03c1455dce7b81eb89797b1d0f714476b188= e6685334 Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 74 ++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 4b712eb4db6f..642af9fcda60 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -21,14 +22,26 @@ #define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) /* 34Kc hardware has 1 block and 1004Kc has 2. */ #define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) +#define ECONET_MAX_IRQS NR_CPUS =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; u32 freq_hz; + int irqs[ECONET_MAX_IRQS]; + int num_irqs; } econet_timer __ro_after_init; =20 static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu); =20 +/* This timer supports two interrupt controller models, either 1 IRQ which= is in per-cpu + * mode which is used on 34Kc CPUs, and separate IRQ number per CPU which = is used on + * 1004Kc CPUs with GIC intc. + */ +static inline bool is_percpu_irq(void) +{ + return econet_timer.num_irqs =3D=3D 1; +} + /* Each memory block has 2 timers, the order of registers is: * CTL, CMR0, CNT0, CMR1, CNT1 */ @@ -98,12 +111,21 @@ static int cevt_init_cpu(uint cpu) struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, cpu); u32 reg; =20 + if (!is_percpu_irq() && cpu >=3D econet_timer.num_irqs) + return -EINVAL; + pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu); =20 reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); iowrite32(reg, reg_ctl(cpu)); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + if (is_percpu_irq()) { + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + } else { + if (irq_force_affinity(econet_timer.irqs[cpu], cpumask_of(cpu))) + pr_warn("%s: failed to set IRQ %d affinity to CPU %d\n", + cd->name, econet_timer.irqs[cpu], cpu); + } =20 /* Do this last because it synchronously configures the timer */ clockevents_config_and_register(cd, econet_timer.freq_hz, @@ -171,6 +193,44 @@ static int __init cevt_init(struct device_node *np) return ret; } =20 +static int __init cevt_init_multi_irq(struct device_node *np) +{ + int i, ret; + + for (i =3D 0; i < econet_timer.num_irqs; i++) { + struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, i); + + econet_timer.irqs[i] =3D irq_of_parse_and_map(np, i); + if (econet_timer.irqs[i] <=3D 0) { + pr_err("%pOFn: irq_of_parse_and_map failed", np); + ret =3D -EINVAL; + goto err_free_irqs; + } + + ret =3D request_irq(econet_timer.irqs[i], cevt_interrupt, + IRQF_TIMER | IRQF_NOBALANCING, + np->name, NULL); + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, + econet_timer.irqs[i], ret); + irq_dispose_mapping(econet_timer.irqs[i]); + goto err_free_irqs; + } + + cevt_setup_clockevent(cd, np, econet_timer.irqs[i], i); + cevt_dev_init(i); + } + + return 0; + +err_free_irqs: + while (--i >=3D 0) { + free_irq(econet_timer.irqs[i], NULL); + irq_dispose_mapping(econet_timer.irqs[i]); + } + return ret; +} + static int __init timer_init(struct device_node *np) { struct clk *clk; @@ -184,6 +244,12 @@ static int __init timer_init(struct device_node *np) =20 econet_timer.freq_hz =3D clk_get_rate(clk); =20 + econet_timer.num_irqs =3D of_irq_count(np); + if (econet_timer.num_irqs <=3D 0 || econet_timer.num_irqs > ECONET_MAX_IR= QS) { + pr_err("%pOFn: invalid IRQ count %d\n", np, econet_timer.num_irqs); + return -EINVAL; + } + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { @@ -202,7 +268,11 @@ static int __init timer_init(struct device_node *np) goto err_unmap; } =20 - ret =3D cevt_init(np); + if (is_percpu_irq()) + ret =3D cevt_init(np); + else + ret =3D cevt_init_multi_irq(np); + if (ret < 0) goto err_unmap; =20 --=20 2.39.5