From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>

for jhb100, While IP assert async reset, it may generate glitch
and propagate to downstream IP. In order to solve RDC issue,
conduct clock gating before asserting reset to prevent generating glitch.

Lianfeng Ouyang (2):
  dt-bindings: Add bindings for StarFive JHB100 SoC trng controller.
  hwrng: starfive: Update clk and reset sequence

 .../bindings/rng/starfive,jh7110-trng.yaml     |  2 +-
 MAINTAINERS                                    |  2 +-
 drivers/char/hw_random/jh7110-trng.c           | 18 ++++++++++++++++--
 3 files changed, 18 insertions(+), 4 deletions(-)

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2.43.0