From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>

for jhb100, While IP assert async reset, it may generate glitch
and propagate to downstream IP. In order to solve RDC issue,
conduct clock gating before asserting reset to prevent generating glitch.

Optimization-driven PM logic. The original driver did not declare PM as
active in the probe, resulting in the count not being able to drop to 0

Lianfeng Ouyang (2):
  dt-bindings: Add bindings for StarFive JHB100 SoC trng controller
  hwrng: starfive: Update clk and reset sequence

 .../bindings/rng/starfive,jh7110-trng.yaml    | 10 +--
 MAINTAINERS                                   |  2 +-
 drivers/char/hw_random/jh7110-trng.c          | 83 ++++++++++++++-----
 3 files changed, 65 insertions(+), 30 deletions(-)

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2.43.0