phy: zynqmp: fix SERDES scrambler register handling and enable for USB

[PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB

Posted by Radhey Shyam Pandey 1 month ago

This series fixes three related issues in the ZynqMP SERDES PHY
scrambler/encoder bypass path:

1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2
   of L0_TX_DIG_61, which is a reserved read-only field. Correct the
   mask to (BIT(3) | GENMASK(1, 0)).

2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which
   performs a full register write, clobbering unrelated bits. Switch
   to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other
   register fields.

3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as
   mandated by the USB 3.x specification. The driver was incorrectly
   bypassing these for USB, the same as SATA and SGMII where encoding
   is handled in the controller.

Nava kishore Manne (3):
  phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
  phy: zynqmp: use read-modify-write for SERDES scrambler bypass
  phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB

 drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)


base-commit: 5d6919055dec134de3c40167a490f33c74c12581
-- 
2.44.4

Re: [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB

Posted by Laurent Pinchart 3 weeks, 3 days ago

Hi Radhey,

I haven't really been involved with the phy-zynqmp driver for a while,
despite still being listed as a maintainer. I have just sent a patch
(you're on CC) to hand maintainership duties over to Tomi Valkeinen, who
took over maintainership of the ZynqMP DPSUB driver. As Tomi isn't
really involved with the PHYs, in particular with the non-DP PHYs
supported by the driver, it could also make more sense for someone from
AMD to take over maintainer duties for phy-zynqmp.

On Mon, May 11, 2026 at 10:01:32PM +0530, Radhey Shyam Pandey wrote:
> This series fixes three related issues in the ZynqMP SERDES PHY
> scrambler/encoder bypass path:
> 
> 1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2
>    of L0_TX_DIG_61, which is a reserved read-only field. Correct the
>    mask to (BIT(3) | GENMASK(1, 0)).
> 
> 2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which
>    performs a full register write, clobbering unrelated bits. Switch
>    to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other
>    register fields.
> 
> 3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as
>    mandated by the USB 3.x specification. The driver was incorrectly
>    bypassing these for USB, the same as SATA and SGMII where encoding
>    is handled in the controller.
> 
> Nava kishore Manne (3):
>   phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
>   phy: zynqmp: use read-modify-write for SERDES scrambler bypass
>   phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB
> 
>  drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++-------
>  1 file changed, 30 insertions(+), 7 deletions(-)
> 
> 
> base-commit: 5d6919055dec134de3c40167a490f33c74c12581

-- 
Regards,

Laurent Pinchart

Re: [PATCH 0/3] phy: zynqmp: fix SERDES scrambler register handling and enable for USB

Posted by Pandey, Radhey Shyam 3 weeks, 3 days ago

On 5/19/2026 1:55 PM, Laurent Pinchart wrote:
> Hi Radhey,
> 
> I haven't really been involved with the phy-zynqmp driver for a while,
> despite still being listed as a maintainer. I have just sent a patch
> (you're on CC) to hand maintainership duties over to Tomi Valkeinen, who
> took over maintainership of the ZynqMP DPSUB driver. As Tomi isn't
> really involved with the PHYs, in particular with the non-DP PHYs
> supported by the driver, it could also make more sense for someone from
> AMD to take over maintainer duties for phy-zynqmp.

Thanks for your continued support. As i am handling this driver
internally will send out a patch to also add myself as maintainer.

Thanks,
Radhey>
> On Mon, May 11, 2026 at 10:01:32PM +0530, Radhey Shyam Pandey wrote:
>> This series fixes three related issues in the ZynqMP SERDES PHY
>> scrambler/encoder bypass path:
>>
>> 1. The L0_TM_DISABLE_SCRAMBLE_ENCODER mask incorrectly included bit 2
>>     of L0_TX_DIG_61, which is a reserved read-only field. Correct the
>>     mask to (BIT(3) | GENMASK(1, 0)).
>>
>> 2. xpsgtr_bypass_scrambler_8b10b() used xpsgtr_write_phy() which
>>     performs a full register write, clobbering unrelated bits. Switch
>>     to xpsgtr_clr_set_phy() with clr=mask, set=mask to preserve other
>>     register fields.
>>
>> 3. USB Gen1 requires PHY-side scrambling and 8b/10b encoding as
>>     mandated by the USB 3.x specification. The driver was incorrectly
>>     bypassing these for USB, the same as SATA and SGMII where encoding
>>     is handled in the controller.
>>
>> Nava kishore Manne (3):
>>    phy: zynqmp: fix L0_TM_DISABLE_SCRAMBLE_ENCODER mask
>>    phy: zynqmp: use read-modify-write for SERDES scrambler bypass
>>    phy: zynqmp: keep SERDES scrambler and 8b/10b enabled for USB
>>
>>   drivers/phy/xilinx/phy-zynqmp.c | 37 ++++++++++++++++++++++++++-------
>>   1 file changed, 30 insertions(+), 7 deletions(-)
>>
>>
>> base-commit: 5d6919055dec134de3c40167a490f33c74c12581
>