[v2] A proposal to add a gpio-locked fixed clock driver.

[PATCH v2 0/2] A proposal to add a gpio-locked fixed clock driver.

Posted by Vyacheslav Yurkov via B4 Relay 1 month ago

A gpio-locked fixed clock aggregates one or more input clocks and/or one
or more GPIOs. It's similar to a gated-fixed-clock, but GPIO direction is
inverted. Consumers can use the output clock to wait until all input
clocks are locked and only then initialize / access dependent peripherals.

The usage example for such a driver is when peripherals depend on PLLs in
a FPGA, which can't be directly accessed by the CPU, but need a GPIO pin
to check whether clock is actually usable. E.g. some of the IPs might not
have a proper split between registers and IP core, which means that if an
external clock and/or PLL lock is missing and one tries to access the 
registers, the response never comes, thus the CPU stalls.

Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
Signed-off-by: Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>
---
Changes in v2:
- Renamed to clk-gpio-locked to express intent.
- Provide enable() / is_enabled() operations so the clock behaves as
  expected
- Fixed DTS errors / warnings
- Link to v1: https://lore.kernel.org/r/20260318-feature-clock-guard-v1-0-6137cb4084b7@bruker.com

---
Vyacheslav Yurkov (2):
      clk: Add gpio-locked clock driver
      dt-bindings: Add GPIO locked fixed clock

 .../bindings/clock/gpio-locked-fixed-clock.yaml    |  77 ++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-gpio-locked.c                      | 306 +++++++++++++++++++++
 3 files changed, 384 insertions(+)
---
base-commit: 917719c412c48687d4a176965d1fa35320ec457c
change-id: 20260318-feature-clock-guard-f20a2c35b965

Best regards,
-- 
Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>

Re: [PATCH v2 0/2] A proposal to add a gpio-locked fixed clock driver.

Posted by Krzysztof Kozlowski 4 weeks, 1 day ago

On Sun, May 10, 2026 at 06:06:21PM +0000, Vyacheslav Yurkov wrote:
> A gpio-locked fixed clock aggregates one or more input clocks and/or one
> or more GPIOs. It's similar to a gated-fixed-clock, but GPIO direction is
> inverted. Consumers can use the output clock to wait until all input
> clocks are locked and only then initialize / access dependent peripherals.
> 
> The usage example for such a driver is when peripherals depend on PLLs in
> a FPGA, which can't be directly accessed by the CPU, but need a GPIO pin
> to check whether clock is actually usable. E.g. some of the IPs might not
> have a proper split between registers and IP core, which means that if an
> external clock and/or PLL lock is missing and one tries to access the 
> registers, the response never comes, thus the CPU stalls.
> 
> Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
> Signed-off-by: Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>
> ---
> Changes in v2:
> - Renamed to clk-gpio-locked to express intent.
> - Provide enable() / is_enabled() operations so the clock behaves as
>   expected
> - Fixed DTS errors / warnings
> - Link to v1: https://lore.kernel.org/r/20260318-feature-clock-guard-v1-0-6137cb4084b7@bruker.com
> 
> ---

Please format your submission properly - read DT bindings submitting
patches, add proper blank lines in the schema, use generic node names so
that we can avoid commenting trivialities.

Best regards,
Krzysztof