drivers/pci/controller/dwc/pci-imx6.c | 6 +-- .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- drivers/pci/controller/dwc/pci-meson.c | 4 +- .../pci/controller/dwc/pcie-designware-ep.c | 4 +- .../pci/controller/dwc/pcie-designware-host.c | 4 +- drivers/pci/controller/dwc/pcie-designware.c | 16 +++--- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++ drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- drivers/pci/controller/dwc/pcie-eswin.c | 3 +- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ 17 files changed, 85 insertions(+), 97 deletions(-)
The DWC PCIe core and its many platform drivers repeatedly call dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the PCI Express Capability structure. This is wasteful and makes the code verbose. And some even search for the PCI_CAP_ID_EXP offset value within the suspend/resume functions. Add a cached pcie_cap field in struct dw_pcie and a helper dw_pcie_get_pcie_cap() to initialize it once at probe time. Then replace all explicit capability searches with the cached value across the entire dwc subtree. Hans Zhang (3): PCI: dwc: Add pcie_cap field and helper in designware header PCI: dwc: Use cached PCIe capability offset in core PCI: dwc: Simplify platform drivers using cached capability offset drivers/pci/controller/dwc/pci-imx6.c | 6 +-- .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- drivers/pci/controller/dwc/pci-meson.c | 4 +- .../pci/controller/dwc/pcie-designware-ep.c | 4 +- .../pci/controller/dwc/pcie-designware-host.c | 4 +- drivers/pci/controller/dwc/pcie-designware.c | 16 +++--- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++ drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- drivers/pci/controller/dwc/pcie-eswin.c | 3 +- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ 17 files changed, 85 insertions(+), 97 deletions(-) base-commit: 70390501d1944d4e5b8f7352be180fceb3a44132 -- 2.34.1
On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: > The DWC PCIe core and its many platform drivers repeatedly call > dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the > PCI Express Capability structure. This is wasteful and makes the code > verbose. And some even search for the PCI_CAP_ID_EXP offset value within > the suspend/resume functions. > Sashiko has flagged some real issues with this series in accessing DBI space very early and 'pci->pcie_cap' being 0. Those needs to be fixed. - Mani > Add a cached pcie_cap field in struct dw_pcie and a helper > dw_pcie_get_pcie_cap() to initialize it once at probe time. Then replace > all explicit capability searches with the cached value across the > entire dwc subtree. > > Hans Zhang (3): > PCI: dwc: Add pcie_cap field and helper in designware header > PCI: dwc: Use cached PCIe capability offset in core > PCI: dwc: Simplify platform drivers using cached capability offset > > drivers/pci/controller/dwc/pci-imx6.c | 6 +-- > .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- > drivers/pci/controller/dwc/pci-meson.c | 4 +- > .../pci/controller/dwc/pcie-designware-ep.c | 4 +- > .../pci/controller/dwc/pcie-designware-host.c | 4 +- > drivers/pci/controller/dwc/pcie-designware.c | 16 +++--- > drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++ > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- > drivers/pci/controller/dwc/pcie-eswin.c | 3 +- > drivers/pci/controller/dwc/pcie-fu740.c | 2 +- > drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- > drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- > drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- > drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- > drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- > drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ > 17 files changed, 85 insertions(+), 97 deletions(-) > > > base-commit: 70390501d1944d4e5b8f7352be180fceb3a44132 > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
On 5/19/26 21:57, Manivannan Sadhasivam wrote: > On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: >> The DWC PCIe core and its many platform drivers repeatedly call >> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the >> PCI Express Capability structure. This is wasteful and makes the code >> verbose. And some even search for the PCI_CAP_ID_EXP offset value within >> the suspend/resume functions. >> > > Sashiko has flagged some real issues with this series in accessing DBI space > very early and 'pci->pcie_cap' being 0. Hi Mani, We have discussed this issue in the Cadence driver. I think it won't cause any problems. Specifically as follows: https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ """ As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are required to implement the PCI Express Capability structure, which must be included somewhere in this linked list. """ Bjorn also responded as follows: https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ """ It's true that all Root Ports must have a PCIe Capability. """ Mani, should I continue to make the judgment that 'pci->pcie_cap' might be 0 as per your instructions? Best regards, Hans > > Those needs to be fixed. > > - Mani > >> Add a cached pcie_cap field in struct dw_pcie and a helper >> dw_pcie_get_pcie_cap() to initialize it once at probe time. Then replace >> all explicit capability searches with the cached value across the >> entire dwc subtree. >> >> Hans Zhang (3): >> PCI: dwc: Add pcie_cap field and helper in designware header >> PCI: dwc: Use cached PCIe capability offset in core >> PCI: dwc: Simplify platform drivers using cached capability offset >> >> drivers/pci/controller/dwc/pci-imx6.c | 6 +-- >> .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- >> drivers/pci/controller/dwc/pci-meson.c | 4 +- >> .../pci/controller/dwc/pcie-designware-ep.c | 4 +- >> .../pci/controller/dwc/pcie-designware-host.c | 4 +- >> drivers/pci/controller/dwc/pcie-designware.c | 16 +++--- >> drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++ >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- >> drivers/pci/controller/dwc/pcie-eswin.c | 3 +- >> drivers/pci/controller/dwc/pcie-fu740.c | 2 +- >> drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- >> drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- >> drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- >> drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- >> drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- >> drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ >> 17 files changed, 85 insertions(+), 97 deletions(-) >> >> >> base-commit: 70390501d1944d4e5b8f7352be180fceb3a44132 >> -- >> 2.34.1 >> >
On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote: > > > On 5/19/26 21:57, Manivannan Sadhasivam wrote: > > On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: > > > The DWC PCIe core and its many platform drivers repeatedly call > > > dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the > > > PCI Express Capability structure. This is wasteful and makes the code > > > verbose. And some even search for the PCI_CAP_ID_EXP offset value within > > > the suspend/resume functions. > > > > > > > Sashiko has flagged some real issues with this series in accessing DBI space > > very early and 'pci->pcie_cap' being 0. > > > Hi Mani, > > We have discussed this issue in the Cadence driver. I think it won't cause > any problems. Specifically as follows: > > https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ > """ > As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are > required to implement the PCI Express Capability structure, which > must be included somewhere in this linked list. > """ > > > > Bjorn also responded as follows: > https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ > """ > It's true that all Root Ports must have a PCIe Capability. > """ > Ok, what about reading the DBI registers very early? - Mani -- மணிவண்ணன் சதாசிவம்
On 5/20/26 00:15, Manivannan Sadhasivam wrote: > On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote: >> >> >> On 5/19/26 21:57, Manivannan Sadhasivam wrote: >>> On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: >>>> The DWC PCIe core and its many platform drivers repeatedly call >>>> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the >>>> PCI Express Capability structure. This is wasteful and makes the code >>>> verbose. And some even search for the PCI_CAP_ID_EXP offset value within >>>> the suspend/resume functions. >>>> >>> >>> Sashiko has flagged some real issues with this series in accessing DBI space >>> very early and 'pci->pcie_cap' being 0. >> >> >> Hi Mani, >> >> We have discussed this issue in the Cadence driver. I think it won't cause >> any problems. Specifically as follows: >> >> https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ >> """ >> As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are >> required to implement the PCI Express Capability structure, which >> must be included somewhere in this linked list. >> """ >> >> >> >> Bjorn also responded as follows: >> https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ >> """ >> It's true that all Root Ports must have a PCIe Capability. >> """ >> > > Ok, what about reading the DBI registers very early? Hi Mani, Yes. I have performed the DBI read register operation at the very beginning of the following code. dw_pcie_ep_init() dw_pcie_get_pcie_cap(pci); dw_pcie_host_init dw_pcie_get_pcie_cap(pci); However, for some glue drivers, they need to configure the registers of the PCIe Express Capability earlier than calling dw_pcie_host_init()/dw_pcie_ep_init(). So, for example, in the file: drivers/pci/controller/dwc/pcie-tegra194.c. Here, it is necessary to find the value of 'pci->pcie_cap' earlier. Then, dw_pcie_host_init()/dw_pcie_ep_init() will no longer search for the offset value of the PCIe Express Capability. Best regards, Hans
On Wed, May 20, 2026 at 12:27:21AM +0800, Hans Zhang wrote: > > > On 5/20/26 00:15, Manivannan Sadhasivam wrote: > > On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote: > > > > > > > > > On 5/19/26 21:57, Manivannan Sadhasivam wrote: > > > > On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: > > > > > The DWC PCIe core and its many platform drivers repeatedly call > > > > > dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the > > > > > PCI Express Capability structure. This is wasteful and makes the code > > > > > verbose. And some even search for the PCI_CAP_ID_EXP offset value within > > > > > the suspend/resume functions. > > > > > > > > > > > > > Sashiko has flagged some real issues with this series in accessing DBI space > > > > very early and 'pci->pcie_cap' being 0. > > > > > > > > > Hi Mani, > > > > > > We have discussed this issue in the Cadence driver. I think it won't cause > > > any problems. Specifically as follows: > > > > > > https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ > > > """ > > > As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are > > > required to implement the PCI Express Capability structure, which > > > must be included somewhere in this linked list. > > > """ > > > > > > > > > > > > Bjorn also responded as follows: > > > https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ > > > """ > > > It's true that all Root Ports must have a PCIe Capability. > > > """ > > > > > > > Ok, what about reading the DBI registers very early? > > Hi Mani, > > Yes. I have performed the DBI read register operation at the very beginning > of the following code. > > > dw_pcie_ep_init() > dw_pcie_get_pcie_cap(pci); > > dw_pcie_host_init > dw_pcie_get_pcie_cap(pci); > These both calls will cause crash on a lot of platforms because these will be reading the DBI registers while the resources are not enabled. - Mani -- மணிவண்ணன் சதாசிவம்
On 5/20/26 00:49, Manivannan Sadhasivam wrote: > On Wed, May 20, 2026 at 12:27:21AM +0800, Hans Zhang wrote: >> >> >> On 5/20/26 00:15, Manivannan Sadhasivam wrote: >>> On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote: >>>> >>>> >>>> On 5/19/26 21:57, Manivannan Sadhasivam wrote: >>>>> On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote: >>>>>> The DWC PCIe core and its many platform drivers repeatedly call >>>>>> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the >>>>>> PCI Express Capability structure. This is wasteful and makes the code >>>>>> verbose. And some even search for the PCI_CAP_ID_EXP offset value within >>>>>> the suspend/resume functions. >>>>>> >>>>> >>>>> Sashiko has flagged some real issues with this series in accessing DBI space >>>>> very early and 'pci->pcie_cap' being 0. >>>> >>>> >>>> Hi Mani, >>>> >>>> We have discussed this issue in the Cadence driver. I think it won't cause >>>> any problems. Specifically as follows: >>>> >>>> https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/ >>>> """ >>>> As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are >>>> required to implement the PCI Express Capability structure, which >>>> must be included somewhere in this linked list. >>>> """ >>>> >>>> >>>> >>>> Bjorn also responded as follows: >>>> https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/ >>>> """ >>>> It's true that all Root Ports must have a PCIe Capability. >>>> """ >>>> >>> >>> Ok, what about reading the DBI registers very early? >> >> Hi Mani, >> >> Yes. I have performed the DBI read register operation at the very beginning >> of the following code. >> >> >> dw_pcie_ep_init() >> dw_pcie_get_pcie_cap(pci); >> >> dw_pcie_host_init >> dw_pcie_get_pcie_cap(pci); >> > > These both calls will cause crash on a lot of platforms because these will be > reading the DBI registers while the resources are not enabled. Hi Mani, Next, I will check all the DBI register-related issues. It will be fixed in the next version. Thank you very much. Best regards, Hans
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