From nobody Sat Jun 13 06:23:04 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79AF438239F; Sat, 9 May 2026 13:52:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778334776; cv=none; b=hsaoD1lscGZejzcgsEpHuFsccdVGTrSp4BnZv1h0PaUXZe+kQbhS/dIr9L+PXyB/GGTb+eX1pGZB5YTw77zZLflCO5KsHU7XNeI2kNG3aGC//VZSM9MaO/ymZqEsTsjrpvT+WxgrRltmSmV9/ENB/qNm/0iDtPA5fOjEUaZ/mhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778334776; c=relaxed/simple; bh=UFi8CqcGrdM1pAGmF4kAgBHhbHA8IisD+Tn5ow/NNJ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bd6lj0REw7nYXNiRxatO1U1DpUXzLEZIFmEuchmjRAtFQRuXWC617AacSsTrnhoXCPPWj4B713EvrW9Gh7v7P+ZOmKebt02Z70m1K+nNdctGqcwxHeE5Qx+zOAblGEAAzkC/KoEeksuODJVohjHyUMwLdpTaW8SyAcjp8mlZUTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Au0TXh4Z; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Au0TXh4Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=LT H5VZR3wbji2shWxUMqCGICYtJFJYr1trTdG4CcqwA=; b=Au0TXh4Zc5TrHQ8/OC ZGsjr7P+w0iJx7MFRGdSSw6hCgJdXQpdZ0P6Y9VbjenliJC6iKlJlWGUJ1DnFc4w wkbsjW1cHk13iEITJDfiJF57uzeZKGWEyUZeBxp7ACJMKSLEOyL/reQY/dEqBEyy IEkq33Cfj1mv6Tbny8VtbKYM0= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wDXLzL8O_9p486jAQ--.37610S3; Sat, 09 May 2026 21:51:58 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/3] PCI: dwc: Add pcie_cap field and helper in designware header Date: Sat, 9 May 2026 21:51:50 +0800 Message-Id: <20260509135152.2241235-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260509135152.2241235-1-18255117159@163.com> References: <20260509135152.2241235-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXLzL8O_9p486jAQ--.37610S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7KFWxCF4kArWUWw4fGr1fXrb_yoW8Ww45pa y3JFySkF48AFWava13AanxZr15tas3ArW7Ga9rKw1SqF9xCFyUGa18AryYyF17Kr4Ikrya kw45t34rCFn8JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zE3CzZUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxB5oDGn-O-4CewAA3U Content-Type: text/plain; charset="utf-8" Add a pcie_cap field to struct dw_pcie to store the offset of the PCI Express Capability structure. Provide a helper dw_pcie_get_pcie_cap() which performs the capability search on first call and caches the result. This is a preparatory step for replacing repetitive capability searches in both core and platform drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 3e69ef60165b..4baf7eb072eb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -568,6 +568,8 @@ struct dw_pcie { * use_parent_dt_ranges to true to avoid this warning. */ bool use_parent_dt_ranges; + + u8 pcie_cap; /* PCIe capability offset */ }; =20 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -805,6 +807,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pci= e *pci) dw_pcie_writel_dbi(pci, reg, val); } =20 +/** + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset + * @pci: DWC instance + * + * Finds and caches the offset of PCI_CAP_ID_EXP on first call. + * Returns 0 if the capability is not present. + */ +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci) +{ + if (!pci->pcie_cap) + pci->pcie_cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + return pci->pcie_cap; +} + static inline int dw_pcie_start_link(struct dw_pcie *pci) { if (pci->ops && pci->ops->start_link) --=20 2.34.1 From nobody Sat Jun 13 06:23:04 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C57D139478B; Sat, 9 May 2026 13:53:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778334785; cv=none; b=g35hY+iFxtQDuquVNWAY+u32CWBt4LZ1IZzpTdtTHgE1D9iX72wE/g2jc4Raan2R/kbsmVHngdOXm8H4v167xV/QfOmyoJtp+RH9dPLXX96UzT2r2HwGO3PqywNLSuGD9caHZyWSfutEzkE5w9XChu5o0q38UIGfDMpcfRxGasQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778334785; c=relaxed/simple; bh=CpTLj9xyX4jvi2On3S9bcw4iCX30in9FUvT/T72EnIM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HoDgovOqvehBf3HHjayiuinEmi5TpEDk+r6IfgJtbLRvI3lFe2p0aqnlPyIunpaxPVRvh9iLJ3pogPV0zSMhp2/7YmXfCaA2AUp6JRFNzh5lvqCw2hVVRg7vj3PSDT9Cb5itokU8rjqOb/OcVaMUnIcqH/fJgJ8k5B8/Mo/MtQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=o9S+Nn+b; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="o9S+Nn+b" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=U4 TGWKaj7SkIQ8cbzabsaYNhoU9LhZdeAI4/egJLJc8=; b=o9S+Nn+bI2btgVgr2A i7Kj1LP7ypYonk+V1R4Yt9bYs7Qjp1t9rBo76rvkF5CUKNiSn+kNsNRHGra2qAiX W+Cona+v7xZwnniYiKzLDaeg6Q7NCoAsYJm98AQiaN1IXc987QbS0BGOKkV/tlB2 d3A/Q4dC0HTCddI3u7Kldu5dQ= Received: from Precision-7960.. (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wDXLzL8O_9p486jAQ--.37610S4; Sat, 09 May 2026 21:51:59 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 2/3] PCI: dwc: Use cached PCIe capability offset in core Date: Sat, 9 May 2026 21:51:51 +0800 Message-Id: <20260509135152.2241235-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260509135152.2241235-1-18255117159@163.com> References: <20260509135152.2241235-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXLzL8O_9p486jAQ--.37610S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxGFWrur15XryUAF18uF1DAwb_yoWrKw1fpa y5JFyYyF18AF45ZFn09as5Zr13tF9xArW7Ca9agr1SvFy2yFWjga18Ary3trn7KFsFyryY 9w18trW5C3Z5tFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zi9a9xUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6x9oDGn-O-+1ZwAA3Q Content-Type: text/plain; charset="utf-8" Modify the DWC core functions to use the cached pcie_cap offset instead of calling dw_pcie_find_capability() each time. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 4 +++- .../pci/controller/dwc/pcie-designware-host.c | 4 +++- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++---------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index d4dc3b24da60..fdcb9012058d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1128,7 +1128,7 @@ static void dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie *pci) * to all other functions as well. */ if (funcs > 1) { - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); func0_lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); func0_lnkcap =3D FIELD_GET(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS, func0_lnkcap); @@ -1390,6 +1390,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msi_msg_addr =3D 0; ep->msi_map_size =3D 0; =20 + dw_pcie_get_pcie_cap(pci); + epc =3D devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "Failed to create epc device\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index c9517a348836..7b3ba83ed616 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -575,6 +575,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 raw_spin_lock_init(&pp->lock); =20 + dw_pcie_get_pcie_cap(pci); + bridge =3D devm_pci_alloc_host_bridge(dev, 0); if (!bridge) return -ENOMEM; @@ -1218,7 +1220,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) =20 int dw_pcie_suspend_noirq(struct dw_pcie *pci) { - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; int ret =3D 0; u32 val; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c11cf61b8319..db62b93c6255 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -761,7 +761,7 @@ const char *dw_pcie_ltssm_status_string(enum dw_pcie_lt= ssm ltssm) */ int dw_pcie_wait_for_link(struct dw_pcie *pci) { - u32 offset, val, ltssm; + u32 val, ltssm; int retries; =20 /* Check if the link is up or not */ @@ -807,8 +807,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) if (pci->max_link_speed > 2) msleep(PCIE_RESET_CONFIG_WAIT_MS); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", FIELD_GET(PCI_EXP_LNKSTA_CLS, val), @@ -844,7 +843,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) { u32 cap, ctrl2, link_speed; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; =20 cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 @@ -890,8 +889,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *= pci) =20 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) { - u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + u32 lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); =20 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); } @@ -899,7 +897,6 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; - u8 cap; =20 if (!num_lanes) return; @@ -936,11 +933,10 @@ static void dw_pcie_link_set_max_link_width(struct dw= _pcie *pci, u32 num_lanes) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); =20 - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); lnkcap &=3D ~PCI_EXP_LNKCAP_MLW; lnkcap |=3D FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, lnkcap); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) --=20 2.34.1 From nobody Sat Jun 13 06:23:04 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A75633F580; 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(unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wDXLzL8O_9p486jAQ--.37610S5; Sat, 09 May 2026 21:52:00 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 3/3] PCI: dwc: Simplify platform drivers using cached capability offset Date: Sat, 9 May 2026 21:51:52 +0800 Message-Id: <20260509135152.2241235-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260509135152.2241235-1-18255117159@163.com> References: <20260509135152.2241235-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXLzL8O_9p486jAQ--.37610S5 X-Coremail-Antispam: 1Uf129KBjvAXoWfCFykJFykWr15uF1kWw48WFg_yoW8uF1fGo Z3Xry8X3W7Gr18XrWIvanxKry7ZwnFv3W5Arn293yDu343A3W5Jr93J3Z8uw12kr4Iyw45 AayDGw1fZFsrWw17n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RRrWFUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wBpDWn-PAC1jgAA3e Content-Type: text/plain; charset="utf-8" Replace explicit dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) calls with the cached pci->pcie_cap in all DWC-based platform drivers: - i.MX6, Layerscape EP, Meson - Rockchip (also remove redundant NULL check and fix typo) - Eswin, Fu740 - Intel Gateway, Qualcomm EP, Qualcomm RC - Sophgo, Spacemit-k1, Spear13xx - Tegra194 (remove private pcie_cap_base) For drivers that need the offset before the core caches it (e.g., ls_pcie_ep_probe), use dw_pcie_get_pcie_cap() to ensure caching. Adjust variable types from u16 to u8 where appropriate. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-imx6.c | 6 +-- .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- drivers/pci/controller/dwc/pci-meson.c | 4 +- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- drivers/pci/controller/dwc/pcie-eswin.c | 3 +- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ 13 files changed, 56 insertions(+), 85 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index e35044cc5218..dc464b460fc1 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -936,10 +936,10 @@ static void imx_pcie_ltssm_enable(struct device *dev) { struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata =3D imx_pcie->drvdata; - u8 offset =3D dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); + struct dw_pcie *pci =3D imx_pcie->pci; u32 tmp; =20 - tmp =3D dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); + tmp =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->lt= ssm_mask, @@ -965,7 +965,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) { struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 tmp; int ret; =20 diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/c= ontroller/dwc/pci-layerscape-ep.c index 8936975ff104..fdb89ae13e4a 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -84,7 +84,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) =20 if (val & PEX_PF0_PME_MES_DR_LUD) { =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); =20 /* * The values of the Maximum Link Width and Supported Link @@ -266,7 +266,7 @@ static int __init ls_pcie_ep_probe(struct platform_devi= ce *pdev) =20 platform_set_drvdata(pdev, pcie); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); pcie->lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 ret =3D dw_pcie_ep_init(&pci->ep); diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 0694084f612b..e8750178fbb0 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -276,7 +276,7 @@ static void meson_set_max_payload(struct meson_pcie *mp= , int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; int max_payload_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); @@ -292,7 +292,7 @@ static void meson_set_max_rd_req_size(struct meson_pcie= *mp, int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; int max_rd_req_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 731d93663cca..9acdc18a573e 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -366,17 +366,14 @@ static void rockchip_pcie_configure_l1ss(struct dw_pc= ie *pci) =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) { - u32 cap, lnkcap; + u32 lnkcap; =20 /* Enable L0S capability for all SoCs */ - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - if (cap) { - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; - dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); - dw_pcie_dbi_ro_wr_dis(pci); - } + lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); + lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); } =20 static int rockchip_pcie_start_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controll= er/dwc/pcie-eswin.c index 2845832b3824..2e5b94c27026 100644 --- a/drivers/pci/controller/dwc/pcie-eswin.c +++ b/drivers/pci/controller/dwc/pcie-eswin.c @@ -84,8 +84,7 @@ static int eswin_pcie_start_link(struct dw_pcie *pci) =20 static bool eswin_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + u16 val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index 66367252032b..553a940e6d89 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -179,7 +179,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev =3D pci->dev; struct fu740_pcie *afp =3D dev_get_drvdata(dev); - u8 cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 cap_exp =3D pci->pcie_cap; int ret; u32 orig, tmp; =20 diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index c21906eced61..939b9dcac7fe 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -121,7 +121,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie = *pcie) static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); + u8 offset =3D pcie->pci.pcie_cap; =20 val =3D pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); =20 diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 257c2bcb5f76..d041189be248 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -307,14 +307,14 @@ static void qcom_pcie_dw_write_dbi2(struct dw_pcie *p= ci, void __iomem *base, static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci =3D &pcie_ep->pci; - u32 offset, status; - int speed, width; - int ret; + int speed, width, ret; + u32 status; + u8 offset; =20 if (!pcie_ep->icc_mem) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); =20 speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); @@ -492,14 +492,13 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) dw_pcie_dbi_ro_wr_en(pci); =20 /* Set the L0s Exit Latency to 2us-4us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); val &=3D ~PCI_EXP_LNKCAP_L0SEL; val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); =20 /* Set the L1 Exit Latency to be 32us-64 us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); val &=3D ~PCI_EXP_LNKCAP_L1EL; val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index af6bf5cce65b..ddb0ae2bf64b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -333,26 +333,22 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); - u16 offset; u32 val; =20 if (!pcie->cfg->no_l0s) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - dw_pcie_dbi_ro_wr_en(pci); =20 - val =3D readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); + val =3D readl(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKCAP); val &=3D ~PCI_EXP_LNKCAP_ASPM_L0S; - writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); + writel(val, pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKCAP); =20 dw_pcie_dbi_ro_wr_dis(pci); } =20 static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; =20 dw_pcie_dbi_ro_wr_en(pci); @@ -362,9 +358,9 @@ static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) * notifications for the Hot-Plug commands. So set the NCCS field to * avoid waiting for the completions. */ - val =3D readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val =3D readl(pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); val |=3D PCI_EXP_SLTCAP_NCCS; - writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + writel(val, pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); =20 dw_pcie_dbi_ro_wr_dis(pci); } @@ -900,7 +896,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; =20 val =3D readl(pcie->parf + PARF_PHY_CTRL); @@ -1209,7 +1205,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pci= e) static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; int i; =20 @@ -1254,8 +1250,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) =20 static bool qcom_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + u16 val =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } @@ -1559,15 +1554,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pci= e) =20 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { - u32 offset, status, width, speed; + u32 status, width, speed; struct dw_pcie *pci =3D pcie->pci; struct dev_pm_opp_key key =3D {}; unsigned long freq_kbps; struct dev_pm_opp *opp; int ret, freq_mbps; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + status =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 /* Only update constraints if link is up. */ if (!(status & PCI_EXP_LNKSTA_DLLLA)) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/control= ler/dwc/pcie-sophgo.c index 044088898819..5a2cd95c6de7 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -164,15 +164,13 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp = *pp) static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 offset, val; - - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; =20 dw_pcie_dbi_ro_wr_en(pci); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset); + val =3D dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + pci->pcie_cap); val &=3D ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); - dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val); + dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + pci->pcie_cap, val); =20 dw_pcie_dbi_ro_wr_dis(pci); } diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index be20a520255b..6f0556336f44 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -114,12 +114,9 @@ static void k1_pcie_disable_resources(struct k1_pcie *= k1) static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) { struct dw_pcie *pci =3D &k1->pci; - u8 offset; + u8 offset =3D pci->pcie_cap + PCI_EXP_LNKCAP; u32 val; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - offset +=3D PCI_EXP_LNKCAP; - dw_pcie_dbi_ro_wr_en(pci); val =3D dw_pcie_readl_dbi(pci, offset); val &=3D ~PCI_EXP_LNKCAP_ASPM_L1; diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/cont= roller/dwc/pcie-spear13xx.c index 01794a9d3ad2..920454266f3f 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -122,7 +122,7 @@ static int spear13xx_pcie_host_init(struct dw_pcie_rp *= pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct spear13xx_pcie *spear13xx_pcie =3D to_spear13xx_pcie(pci); - u32 exp_cap_off =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; =20 spear13xx_pcie->app_base =3D pci->dbi_base + 0x2000; @@ -132,9 +132,9 @@ static int spear13xx_pcie_host_init(struct dw_pcie_rp *= pp) * default value in capability register is 512 bytes. So force * it to 128 here. */ - val =3D dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL); + val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_DEVCTL); val &=3D ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val); + dw_pcie_writew_dbi(pci, offset + PCI_EXP_DEVCTL, val); =20 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80); diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 9dcfa194050e..0d5a5e9027d9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -268,7 +268,6 @@ struct tegra_pcie_dw { u32 num_lanes; u32 cid; u32 ras_des_cap; - u32 pcie_cap_base; u32 aspm_cmrt; u32 aspm_pwr_on_t; u32 aspm_l0s_enter_lat; @@ -312,7 +311,7 @@ static void tegra_pcie_icc_set(struct tegra_pcie_dw *pc= ie) struct dw_pcie *pci =3D &pcie->pci; u32 val, speed, width; =20 - val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, val); width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, val); @@ -340,22 +339,22 @@ static void apply_bad_link_workaround(struct dw_pcie_= rp *pp) * stable anyway, not waiting to confirm if link is really * transitioning to Gen-2 speed */ - val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); if (val & PCI_EXP_LNKSTA_LBMS) { current_link_width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, val); if (pcie->init_link_width > current_link_width) { dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); - val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL2); val &=3D ~PCI_EXP_LNKCTL2_TLS; val |=3D PCI_EXP_LNKCTL2_TLS_2_5GT; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL2, val); =20 - val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL); val |=3D PCI_EXP_LNKCTL_RL; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL, val); } } @@ -399,17 +398,17 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq,= void *arg) apply_bad_link_workaround(pp); } if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) { - val_w =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + + val_w =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); val_w |=3D PCI_EXP_LNKSTA_LBMS; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA, val_w); =20 appl_writel(pcie, APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS, APPL_INTR_STATUS_L1_8_0); =20 - val_w =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + + val_w =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & PCI_EXP_LNKSTA_CLS); @@ -675,7 +674,7 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) =20 l1ss =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); =20 - pcie->ras_des_cap =3D dw_pcie_find_ext_capability(&pcie->pci, + pcie->ras_des_cap =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_VNDR); =20 /* Enable ASPM counters */ @@ -766,15 +765,12 @@ static void tegra_pcie_enable_system_interrupts(struc= t dw_pcie_rp *pp) appl_writel(pcie, val, APPL_INTR_EN_L1_18); } =20 - val_w =3D dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); + val_w =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); pcie->init_link_width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); =20 - val_w =3D dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + - PCI_EXP_LNKCTL); + val_w =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL); val_w |=3D PCI_EXP_LNKCTL_LBMIE; - dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, - val_w); + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCTL, val_w); } =20 static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp) @@ -903,10 +899,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *= pp) =20 pp->bridge->ops =3D &tegra_pci_ops; =20 - if (!pcie->pcie_cap_base) - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); - val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); @@ -927,10 +919,9 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *= pp) =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { - val_16 =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); + val_16 =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); val_16 &=3D ~PCI_EXP_LNKSTA_SLC; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA, val_16); } =20 @@ -1047,8 +1038,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *p= ci) =20 static bool tegra_pcie_dw_link_up(struct dw_pcie *pci) { - struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); - u32 val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); + u32 val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } @@ -1878,16 +1868,13 @@ static void pex_ep_event_pex_rst_deassert(struct te= gra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); } =20 - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + dw_pcie_get_pcie_cap(pci); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { - val_16 =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); + val_16 =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); val_16 &=3D ~PCI_EXP_LNKSTA_SLC; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, - val_16); + dw_pcie_writew_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA, val_16); } =20 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); --=20 2.34.1