[PATCH v4 00/29] soc/qcom/ubwc: rework UBWC configuration database

Dmitry Baryshkov posted 29 patches 1 month ago
There is a newer version of this series
drivers/gpu/drm/msm/adreno/a5xx_gpu.c       |  11 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c       |  93 +--------
drivers/gpu/drm/msm/adreno/a8xx_gpu.c       |  50 +++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c     |   4 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h     |   5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  39 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   |   3 +-
drivers/gpu/drm/msm/msm_mdss.c              | 120 ++++--------
drivers/soc/qcom/ubwc_config.c              | 294 +++++++---------------------
include/linux/soc/qcom/ubwc.h               | 103 ++++++----
10 files changed, 235 insertions(+), 487 deletions(-)
[PATCH v4 00/29] soc/qcom/ubwc: rework UBWC configuration database
Posted by Dmitry Baryshkov 1 month ago
Currently we store several settings in the configuration database. Some
of them are incorrect or not completely matching the expected
configuration settings. Others are directly derivable from the UBWC
version. Rework how we handle the values in the database, trimming it
down to the UBWC version, HBB and several flags.

The series includes patches for drm/msm as well as for the soc/qcom. My
suggestion would be to either create an immutable tag for the first
batch of soc/qcom patches, which we can pull into drm/msm or to ack
merging the first patches through drm/msm tree directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Changes in v4:
- Rebased on linux-next, dropping merged dependencies.
- Reworked A8xx, simplifying several corner cases.
- Link to v3: https://lore.kernel.org/r/20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com

Changes in v3:
- Corrected UWBC_STATIC programming for MDSS 5.x platforms (Konrad)
- Switched MDSS 6.x+ to qcom_ubwc_min_acc_length_64b() too
- Added qcom_ubwc_enable_amsbc() helper
- Reworked the DPU handling of UBWC config, making it simpler to handle
  minor revisions.
- Removed the comment regarding the best guess for min_acc_length
- Link to v2: https://lore.kernel.org/r/20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com

Changes in v2:
- Renamed MDSS UBWC programming function to make it more obvious that
  they are related to the MDSS revision rather than UBWC version
  (Konrad)
- Brought back the patch to use qcom_ubwc_version_tag() in msm_mdss.c,
  got lost in rebases (Konrad)
- Link to v1: https://lore.kernel.org/r/20260306-ubwc-rework-v1-0-9cfdff12f2bb@oss.qualcomm.com

---
Dmitry Baryshkov (28):
      drm/msm/mdss: correct UBWC programming sequences
      soc: qcom: ubwc: define UBWC 3.1
      soc: qcom: ubwc: define helper for MDSS and Adreno drivers
      soc: qcom: ubwc: add helper controlling AMSBC enablement
      drm/msm/adreno: use qcom_ubwc_version_tag() helper
      drm/msm/mdss: use qcom_ubwc_version_tag() helper
      drm/msm/adreno: use new helper to set min_acc length
      drm/msm/mdss: use new helper to set min_acc length
      drm/msm/adreno: use new helper to set macrotile_mode
      drm/msm/mdss: use new helper to set macrotile_mode
      drm/msm/mdss: use new helper to set UBWC bank spreading
      drm/msm/adreno: use new helper to set ubwc_swizzle
      drm/msm/dpu: use new helper to set ubwc_swizzle
      drm/msm/mdss: use new helper to set ubwc_swizzle
      drm/msm/adreno: write reserved UBWC-related bits
      drm/msm/adreno: set fp16compoptdis for UBWC 3.0 formats
      drm/msm/adreno: use new helper to set amsbc
      drm/msm/adreno: use version ranges in A8xx UBWC code
      drm/msm/mdss: use new helper to set amsbc
      drm/msm/dpu: drop ubwc_dec_version
      drm/msm/dpu: invert the order of UBWC checks
      soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targets
      soc: qcom: ubwc: drop ubwc_dec_version
      soc: qcom: ubwc: drop ubwc_bank_spread
      soc: qcom: ubwc: drop macrotile_mode from the database
      soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0
      soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings
      soc: qcom: ubwc: deduplicate UBWC configuration data

Konrad Dybcio (1):
      drm/msm/adreno: Trust the SSoT UBWC config

 drivers/gpu/drm/msm/adreno/a5xx_gpu.c       |  11 +-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c       |  93 +--------
 drivers/gpu/drm/msm/adreno/a8xx_gpu.c       |  50 +++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.c     |   4 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h     |   5 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  39 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   |   3 +-
 drivers/gpu/drm/msm/msm_mdss.c              | 120 ++++--------
 drivers/soc/qcom/ubwc_config.c              | 294 +++++++---------------------
 include/linux/soc/qcom/ubwc.h               | 103 ++++++----
 10 files changed, 235 insertions(+), 487 deletions(-)
---
base-commit: 735d2f48cadaa9a87e7c7601667878de70c771c5
change-id: 20260211-ubwc-rework-e6ce1d8eb520
prerequisite-patch-id: 5bc7dddd09fcdb4f534f8468ab3ad51781667066

Best regards,
--  
With best wishes
Dmitry
Re: [PATCH v4 00/29] soc/qcom/ubwc: rework UBWC configuration database
Posted by Bjorn Andersson 3 weeks, 1 day ago
On Thu, May 07, 2026 at 04:02:56PM +0300, Dmitry Baryshkov wrote:
> Currently we store several settings in the configuration database. Some
> of them are incorrect or not completely matching the expected
> configuration settings. Others are directly derivable from the UBWC
> version. Rework how we handle the values in the database, trimming it
> down to the UBWC version, HBB and several flags.
> 
> The series includes patches for drm/msm as well as for the soc/qcom. My
> suggestion would be to either create an immutable tag for the first
> batch of soc/qcom patches, which we can pull into drm/msm or to ack
> merging the first patches through drm/msm tree directly.
> 

You can find the initial UBWC patches at:

  https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git 20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com

Regards,
Bjorn

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> Changes in v4:
> - Rebased on linux-next, dropping merged dependencies.
> - Reworked A8xx, simplifying several corner cases.
> - Link to v3: https://lore.kernel.org/r/20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com
> 
> Changes in v3:
> - Corrected UWBC_STATIC programming for MDSS 5.x platforms (Konrad)
> - Switched MDSS 6.x+ to qcom_ubwc_min_acc_length_64b() too
> - Added qcom_ubwc_enable_amsbc() helper
> - Reworked the DPU handling of UBWC config, making it simpler to handle
>   minor revisions.
> - Removed the comment regarding the best guess for min_acc_length
> - Link to v2: https://lore.kernel.org/r/20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com
> 
> Changes in v2:
> - Renamed MDSS UBWC programming function to make it more obvious that
>   they are related to the MDSS revision rather than UBWC version
>   (Konrad)
> - Brought back the patch to use qcom_ubwc_version_tag() in msm_mdss.c,
>   got lost in rebases (Konrad)
> - Link to v1: https://lore.kernel.org/r/20260306-ubwc-rework-v1-0-9cfdff12f2bb@oss.qualcomm.com
> 
> ---
> Dmitry Baryshkov (28):
>       drm/msm/mdss: correct UBWC programming sequences
>       soc: qcom: ubwc: define UBWC 3.1
>       soc: qcom: ubwc: define helper for MDSS and Adreno drivers
>       soc: qcom: ubwc: add helper controlling AMSBC enablement
>       drm/msm/adreno: use qcom_ubwc_version_tag() helper
>       drm/msm/mdss: use qcom_ubwc_version_tag() helper
>       drm/msm/adreno: use new helper to set min_acc length
>       drm/msm/mdss: use new helper to set min_acc length
>       drm/msm/adreno: use new helper to set macrotile_mode
>       drm/msm/mdss: use new helper to set macrotile_mode
>       drm/msm/mdss: use new helper to set UBWC bank spreading
>       drm/msm/adreno: use new helper to set ubwc_swizzle
>       drm/msm/dpu: use new helper to set ubwc_swizzle
>       drm/msm/mdss: use new helper to set ubwc_swizzle
>       drm/msm/adreno: write reserved UBWC-related bits
>       drm/msm/adreno: set fp16compoptdis for UBWC 3.0 formats
>       drm/msm/adreno: use new helper to set amsbc
>       drm/msm/adreno: use version ranges in A8xx UBWC code
>       drm/msm/mdss: use new helper to set amsbc
>       drm/msm/dpu: drop ubwc_dec_version
>       drm/msm/dpu: invert the order of UBWC checks
>       soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targets
>       soc: qcom: ubwc: drop ubwc_dec_version
>       soc: qcom: ubwc: drop ubwc_bank_spread
>       soc: qcom: ubwc: drop macrotile_mode from the database
>       soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0
>       soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings
>       soc: qcom: ubwc: deduplicate UBWC configuration data
> 
> Konrad Dybcio (1):
>       drm/msm/adreno: Trust the SSoT UBWC config
> 
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c       |  11 +-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c       |  93 +--------
>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c       |  50 +++--
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c     |   4 +-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h     |   5 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  39 ++--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   |   3 +-
>  drivers/gpu/drm/msm/msm_mdss.c              | 120 ++++--------
>  drivers/soc/qcom/ubwc_config.c              | 294 +++++++---------------------
>  include/linux/soc/qcom/ubwc.h               | 103 ++++++----
>  10 files changed, 235 insertions(+), 487 deletions(-)
> ---
> base-commit: 735d2f48cadaa9a87e7c7601667878de70c771c5
> change-id: 20260211-ubwc-rework-e6ce1d8eb520
> prerequisite-patch-id: 5bc7dddd09fcdb4f534f8468ab3ad51781667066
> 
> Best regards,
> --  
> With best wishes
> Dmitry
>
Re: [PATCH v4 00/29] soc/qcom/ubwc: rework UBWC configuration database
Posted by Dmitry Baryshkov 3 weeks, 2 days ago
On Thu, 07 May 2026 16:02:56 +0300, Dmitry Baryshkov wrote:
> Currently we store several settings in the configuration database. Some
> of them are incorrect or not completely matching the expected
> configuration settings. Others are directly derivable from the UBWC
> version. Rework how we handle the values in the database, trimming it
> down to the UBWC version, HBB and several flags.
> 
> The series includes patches for drm/msm as well as for the soc/qcom. My
> suggestion would be to either create an immutable tag for the first
> batch of soc/qcom patches, which we can pull into drm/msm or to ack
> merging the first patches through drm/msm tree directly.
> 
> [...]

Applied to msm-next, thanks!

[01/29] drm/msm/mdss: correct UBWC programming sequences
        https://gitlab.freedesktop.org/lumag/msm/-/commit/93e1290f429d

Best regards,
-- 
With best wishes
Dmitry
Re: (subset) [PATCH v4 00/29] soc/qcom/ubwc: rework UBWC configuration database
Posted by Bjorn Andersson 3 weeks, 1 day ago
On Thu, 07 May 2026 16:02:56 +0300, Dmitry Baryshkov wrote:
> Currently we store several settings in the configuration database. Some
> of them are incorrect or not completely matching the expected
> configuration settings. Others are directly derivable from the UBWC
> version. Rework how we handle the values in the database, trimming it
> down to the UBWC version, HBB and several flags.
> 
> The series includes patches for drm/msm as well as for the soc/qcom. My
> suggestion would be to either create an immutable tag for the first
> batch of soc/qcom patches, which we can pull into drm/msm or to ack
> merging the first patches through drm/msm tree directly.
> 
> [...]

Applied, thanks!

[02/29] soc: qcom: ubwc: define UBWC 3.1
        commit: ab7e4d7cf6f8efd37a675a85eb0aef3d6a4954ba
[03/29] soc: qcom: ubwc: define helper for MDSS and Adreno drivers
        commit: b5f7365c44d8fd58ef0224bf4111805c4fea0a1e
[04/29] soc: qcom: ubwc: add helper controlling AMSBC enablement
        commit: c5e3f2a3abcb925f0364df09abfd759ff0590454

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>