The AX45MP-specific cache binding is renamed to a generic Last Level
Cache (LLC) schema, as the driver now supports more Andes CPU cores
beyond just AX45MP.
Updated compatible strings:
andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
andestech,ax45mp-cache -> andestech,llcache
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
...ache.yaml => andestech,andes-llcache.yaml} | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%)
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
similarity index 76%
rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
rename to Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
index b135ffa4ab6b..5b97625edd37 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
@@ -2,17 +2,17 @@
# Copyright (C) 2023 Renesas Electronics Corp.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Andestech AX45MP L2 Cache Controller
+title: Andestech Last Level Cache Controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
- A level-2 cache (L2C) is used to improve the system performance by providing
- a large amount of cache line entries and reasonable access delays. The L2C
+ A last level cache (LLC) is used to improve the system performance by providing
+ a large amount of cache line entries and reasonable access delays. The LLC
is shared between cores, and a non-inclusive non-exclusive policy is used.
select:
@@ -20,7 +20,7 @@ select:
compatible:
contains:
enum:
- - andestech,ax45mp-cache
+ - andestech,llcache
required:
- compatible
@@ -29,9 +29,9 @@ properties:
compatible:
items:
- enum:
- - andestech,qilai-ax45mp-cache
- - renesas,r9a07g043f-ax45mp-cache
- - const: andestech,ax45mp-cache
+ - andestech,qilai-llcache
+ - renesas,r9a07g043f-llcache
+ - const: andestech,llcache
- const: cache
reg:
@@ -73,7 +73,7 @@ allOf:
properties:
compatible:
contains:
- const: andestech,qilai-ax45mp-cache
+ const: andestech,qilai-llcache
then:
properties:
@@ -91,7 +91,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
cache-controller@13400000 {
- compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
+ compatible = "renesas,r9a07g043f-llcache", "andestech,llcache",
"cache";
reg = <0x13400000 0x100000>;
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1On Mon, Mar 30, 2026 at 06:27:22PM +0800, Hui Min Mina Chou wrote:
> The AX45MP-specific cache binding is renamed to a generic Last Level
> Cache (LLC) schema, as the driver now supports more Andes CPU cores
> beyond just AX45MP.
>
> Updated compatible strings:
> andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
> renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> andestech,ax45mp-cache -> andestech,llcache
>
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> ---
> ...ache.yaml => andestech,andes-llcache.yaml} | 20 +++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
> rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%)
>
> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
> similarity index 76%
> rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> rename to Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
> index b135ffa4ab6b..5b97625edd37 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
> @@ -2,17 +2,17 @@
> # Copyright (C) 2023 Renesas Electronics Corp.
> %YAML 1.2
> ---
> -$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
> +$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Andestech AX45MP L2 Cache Controller
> +title: Andestech Last Level Cache Controller
>
> maintainers:
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> description:
> - A level-2 cache (L2C) is used to improve the system performance by providing
> - a large amount of cache line entries and reasonable access delays. The L2C
> + A last level cache (LLC) is used to improve the system performance by providing
> + a large amount of cache line entries and reasonable access delays. The LLC
> is shared between cores, and a non-inclusive non-exclusive policy is used.
>
> select:
> @@ -20,7 +20,7 @@ select:
> compatible:
> contains:
> enum:
> - - andestech,ax45mp-cache
> + - andestech,llcache
>
> required:
> - compatible
> @@ -29,9 +29,9 @@ properties:
> compatible:
> items:
> - enum:
> - - andestech,qilai-ax45mp-cache
> - - renesas,r9a07g043f-ax45mp-cache
> - - const: andestech,ax45mp-cache
> + - andestech,qilai-llcache
> + - renesas,r9a07g043f-llcache
> + - const: andestech,llcache
> - const: cache
If you want to add a more generalied compatible to use as a fallback,
insert it underneath andestech,ax45mp-cache. andestech,llcache is far
too generic though, and there appears to be no user that isn't an ax45mp
now anyway, so not sure what this even gives us right now?
On 30/03/2026 12:27, Hui Min Mina Chou wrote: > The AX45MP-specific cache binding is renamed to a generic Last Level > Cache (LLC) schema, as the driver now supports more Andes CPU cores > beyond just AX45MP. > > Updated compatible strings: > andestech,qilai-ax45mp-cache -> andestech,qilai-llcache > renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache > andestech,ax45mp-cache -> andestech,llcache Why? No explanations and that is clear ABI break. = Best regards, Krzysztof
On Mon, Mar 30, 2026 at 03:00:41PM +0200, Krzysztof Kozlowski wrote: > On 30/03/2026 12:27, Hui Min Mina Chou wrote: > > The AX45MP-specific cache binding is renamed to a generic Last Level > > Cache (LLC) schema, as the driver now supports more Andes CPU cores > > beyond just AX45MP. > > > > Updated compatible strings: > > andestech,qilai-ax45mp-cache -> andestech,qilai-llcache > > renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache > > andestech,ax45mp-cache -> andestech,llcache > > Why? No explanations and that is clear ABI break. Ye, I am not going to accept any compatible string renames for this hardware. The break is too significant, since the devices *need* this to function.
On Mon, 30 Mar 2026 18:27:22 +0800, Hui Min Mina Chou wrote:
> The AX45MP-specific cache binding is renamed to a generic Last Level
> Cache (LLC) schema, as the driver now supports more Andes CPU cores
> beyond just AX45MP.
>
> Updated compatible strings:
> andestech,qilai-ax45mp-cache -> andestech,qilai-llcache
> renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache
> andestech,ax45mp-cache -> andestech,llcache
>
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> ---
> ...ache.yaml => andestech,andes-llcache.yaml} | 20 +++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
> rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename
$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml
file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260330102724.1012470-6-minachou@andestech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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