From nobody Thu Apr 2 05:51:08 2026 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 819AE1FF5E3 for ; Mon, 30 Mar 2026 10:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867679; cv=none; b=fijLRRx0+gAJFvw6SPi6SLu8tj73YkgizTlh96ll67Ls6kaqQ5rbqKMPwMhz1zWmB+/cC0YyOzwjevEKMFlj3xSIFCJ1y1ZM1a4HKiGxSRHLKMvD8ik80bcd2HnO7BaOTQNB8rSXNQrKsh/Gm6dREoAKd4Kxj8Ygzynu/oiGoDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867679; c=relaxed/simple; bh=MFNlQBask5tlbqzXB2h6hAi9KVM4XqNTR+M9bQFxOkw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J+zxbyxoPGaLjm2b5gd25F/9kiMPgARY6INbFTS180lko2nxxk+GLMvqn/IPA5SwQ55F9ZAMP76m3uzId1IqoGrJbyTez7gusXBYZn5ODwWakjy+cJn/Rdw5pt4Nt2NVIFM8NmCd9rqTa/kixSikQNasFW/2/8XRfScp0UDDVyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UASpr4039455 for ; Mon, 30 Mar 2026 18:28:51 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UASGfH038279; Mon, 30 Mar 2026 18:28:16 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:16 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 5/7] dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache Date: Mon, 30 Mar 2026 18:27:22 +0800 Message-ID: <20260330102724.1012470-6-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 62UASpr4039455 Content-Type: text/plain; charset="utf-8" The AX45MP-specific cache binding is renamed to a generic Last Level Cache (LLC) schema, as the driver now supports more Andes CPU cores beyond just AX45MP. Updated compatible strings: andestech,qilai-ax45mp-cache -> andestech,qilai-llcache renesas,r9a07g043f-ax45mp-cache -> renesas,r9a07g043f-llcache andestech,ax45mp-cache -> andestech,llcache Signed-off-by: Hui Min Mina Chou --- ...ache.yaml =3D> andestech,andes-llcache.yaml} | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yam= l =3D> andestech,andes-llcache.yaml} (76%) diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache= .yaml b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml similarity index 76% rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.= yaml rename to Documentation/devicetree/bindings/cache/andestech,andes-llcache.y= aml index b135ffa4ab6b..5b97625edd37 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,andes-llcache.yaml @@ -2,17 +2,17 @@ # Copyright (C) 2023 Renesas Electronics Corp. %YAML 1.2 --- -$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Andestech AX45MP L2 Cache Controller +title: Andestech Last Level Cache Controller =20 maintainers: - Lad Prabhakar =20 description: - A level-2 cache (L2C) is used to improve the system performance by provi= ding - a large amount of cache line entries and reasonable access delays. The L= 2C + A last level cache (LLC) is used to improve the system performance by pr= oviding + a large amount of cache line entries and reasonable access delays. The L= LC is shared between cores, and a non-inclusive non-exclusive policy is use= d. =20 select: @@ -20,7 +20,7 @@ select: compatible: contains: enum: - - andestech,ax45mp-cache + - andestech,llcache =20 required: - compatible @@ -29,9 +29,9 @@ properties: compatible: items: - enum: - - andestech,qilai-ax45mp-cache - - renesas,r9a07g043f-ax45mp-cache - - const: andestech,ax45mp-cache + - andestech,qilai-llcache + - renesas,r9a07g043f-llcache + - const: andestech,llcache - const: cache =20 reg: @@ -73,7 +73,7 @@ allOf: properties: compatible: contains: - const: andestech,qilai-ax45mp-cache + const: andestech,qilai-llcache =20 then: properties: @@ -91,7 +91,7 @@ examples: #include =20 cache-controller@13400000 { - compatible =3D "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45m= p-cache", + compatible =3D "renesas,r9a07g043f-llcache", "andestech,llcache", "cache"; reg =3D <0x13400000 0x100000>; interrupts =3D <508 IRQ_TYPE_LEVEL_HIGH>; --=20 2.34.1