[PATCH v6 48/90] x86/cpu/hygon: Use parsed CPUID(0x80000005) and CPUID(0x80000006)

Ahmed S. Darwish posted 90 patches 6 days, 16 hours ago
[PATCH v6 48/90] x86/cpu/hygon: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
Posted by Ahmed S. Darwish 6 days, 16 hours ago
For Hygon init, use parsed CPUID(0x80000005) and CPUID(0x80000006) instead
of direct CPUID queries and ugly bitwise operations.

Consolidate all comments; the code has now clear logic and bitfield names.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/hygon.c | 35 ++++++++++++++++-------------------
 1 file changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 3e8891a9caf2..4a63538c2b3f 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -229,35 +229,32 @@ static void init_hygon(struct cpuinfo_x86 *c)
 	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
 }
 
+/*
+ * For DTLB/ITLB 2M-4M detection, fall back to L1 if L2 is disabled
+ */
 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
 {
-	u32 ebx, eax, ecx, edx;
-	u16 mask = 0xfff;
+	const struct leaf_0x80000005_0 *el5 = cpuid_leaf(c, 0x80000005);
+	const struct leaf_0x80000006_0 *el6 = cpuid_leaf(c, 0x80000006);
 
-	if (c->extended_cpuid_level < 0x80000006)
+	if (!el5 || !el6)
 		return;
 
-	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
+	tlb_lld_4k = el6->l2_dtlb_4k_nentries;
+	tlb_lli_4k = el6->l2_itlb_4k_nentries;
 
-	tlb_lld_4k = (ebx >> 16) & mask;
-	tlb_lli_4k = ebx & mask;
+	if (el6->l2_dtlb_2m_4m_nentries)
+		tlb_lld_2m = el6->l2_dtlb_2m_4m_nentries;
+	else
+		tlb_lld_2m = el5->l1_dtlb_2m_4m_nentries;
 
-	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
-	if (!((eax >> 16) & mask))
-		tlb_lld_2m = (cpuid_eax(0x80000005) >> 16) & 0xff;
+	if (el6->l2_itlb_2m_4m_nentries)
+		tlb_lli_2m = el6->l2_itlb_2m_4m_nentries;
 	else
-		tlb_lld_2m = (eax >> 16) & mask;
+		tlb_lli_2m = el5->l1_itlb_2m_4m_nentries;
 
-	/* a 4M entry uses two 2M entries */
+	/* A 4M TLB entry uses two 2M entries */
 	tlb_lld_4m = tlb_lld_2m >> 1;
-
-	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
-	if (!(eax & mask)) {
-		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
-		tlb_lli_2m = eax & 0xff;
-	} else
-		tlb_lli_2m = eax & mask;
-
 	tlb_lli_4m = tlb_lli_2m >> 1;
 }
 
-- 
2.53.0