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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 48/90] x86/cpu/hygon: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:16:02 +0100 Message-ID: <20260327021645.555257-49-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Hygon init, use parsed CPUID(0x80000005) and CPUID(0x80000006) instead of direct CPUID queries and ugly bitwise operations. Consolidate all comments; the code has now clear logic and bitfield names. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/hygon.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 3e8891a9caf2..4a63538c2b3f 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -229,35 +229,32 @@ static void init_hygon(struct cpuinfo_x86 *c) clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); } =20 +/* + * For DTLB/ITLB 2M-4M detection, fall back to L1 if L2 is disabled + */ static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) { - u32 ebx, eax, ecx, edx; - u16 mask =3D 0xfff; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); =20 - if (c->extended_cpuid_level < 0x80000006) + if (!el5 || !el6) return; =20 - cpuid(0x80000006, &eax, &ebx, &ecx, &edx); + tlb_lld_4k =3D el6->l2_dtlb_4k_nentries; + tlb_lli_4k =3D el6->l2_itlb_4k_nentries; =20 - tlb_lld_4k =3D (ebx >> 16) & mask; - tlb_lli_4k =3D ebx & mask; + if (el6->l2_dtlb_2m_4m_nentries) + tlb_lld_2m =3D el6->l2_dtlb_2m_4m_nentries; + else + tlb_lld_2m =3D el5->l1_dtlb_2m_4m_nentries; =20 - /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!((eax >> 16) & mask)) - tlb_lld_2m =3D (cpuid_eax(0x80000005) >> 16) & 0xff; + if (el6->l2_itlb_2m_4m_nentries) + tlb_lli_2m =3D el6->l2_itlb_2m_4m_nentries; else - tlb_lld_2m =3D (eax >> 16) & mask; + tlb_lli_2m =3D el5->l1_itlb_2m_4m_nentries; =20 - /* a 4M entry uses two 2M entries */ + /* A 4M TLB entry uses two 2M entries */ tlb_lld_4m =3D tlb_lld_2m >> 1; - - /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!(eax & mask)) { - cpuid(0x80000005, &eax, &ebx, &ecx, &edx); - tlb_lli_2m =3D eax & 0xff; - } else - tlb_lli_2m =3D eax & mask; - tlb_lli_4m =3D tlb_lli_2m >> 1; } =20 --=20 2.53.0