Force-enabling Centaur/Zhaoxin CPU features through MSR writes leads to the
CPUID(0xc0000001) EDX feature flags getting changed.

Rescan CPUID(0xc0000001) in that case.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/centaur.c | 6 ++++--
 arch/x86/kernel/cpu/zhaoxin.c | 5 +++--
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 681d2da49341..a97e38fa6a9f 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -44,9 +44,11 @@ static void init_c3(struct cpuinfo_x86 *c)
 			pr_info("CPU: Enabled h/w RNG\n");
 		}
 
-		/* store Centaur Extended Feature Flags as
-		 * word 5 of the CPU capability bit array
+		/*
+		 * Force-enabling CPU features affects the CPUID(0xc0000001)
+		 * EDX feature bits.  Refresh the leaf.
 		 */
+		cpuid_refresh_leaf(c, 0xc0000001);
 		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
 	}
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 761aef5590ac..55bc656aaa95 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -46,9 +46,10 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
 		}
 
 		/*
-		 * Store Extended Feature Flags as word 5 of the CPU
-		 * capability bit array
+		 * Force-enabling CPU features affects the CPUID(0xc0000001)
+		 * EDX feature bits.  Refresh the leaf.
 		 */
+		cpuid_refresh_leaf(c, 0xc0000001);
 		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
 	}
 
-- 
2.53.0