From: Biju Das <biju.das.jz@bp.renesas.com>
The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add
tint_start variable in struct rzg2l_hw_info to handle this difference
and drop the macro IRQC_TINT_START.
While at it, update the variable type of titseln, tssr_offset, tssr_index,
index, and sense to unsigned int, in rzg2l_tint_set_edge() as these
variables are used only for calculation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v6->v7:
* No change.
v5->v6:
* Updated the variable type of titseln, tssr_offset, tssr_index, index,
and sense to unsigned int, in rzg2l_tint_set_edge() as these variables
are used only for calculation.
* Updated commit description.
v4->v5:
* Dropped the hw_irq range check involving info.tint_start
v3->v4:
* Updated commit description 'this differences->this difference'.
* Updated tint_start variable type from u8-> unsigned int.
v2->v3:
* No change
v1->v2:
* No change
---
drivers/irqchip/irq-renesas-rzg2l.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 2b7a70bdcba1..e5543aea86b4 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -22,7 +22,6 @@
#define IRQC_IRQ_START 1
#define IRQC_IRQ_COUNT 8
-#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
#define IRQC_TINT_COUNT 32
#define ISCR 0x10
@@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache {
/**
* struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tint_start: Start of TINT interrupts
* @num_irq: Total Number of interrupts
*/
struct rzg2l_hw_info {
+ unsigned int tint_start;
unsigned int num_irq;
};
@@ -125,7 +126,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq
static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info.tint_start);
u32 reg;
reg = readl_relaxed(priv->base + TSCR);
@@ -180,7 +181,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info.tint_start);
writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK);
}
@@ -188,7 +189,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info.tint_start);
writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK);
}
@@ -253,7 +254,7 @@ static void rzfive_tint_endisable(struct irq_data *d, bool enable)
{
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
- unsigned int offset = hwirq - IRQC_TINT_START;
+ unsigned int offset = hwirq - priv->info.tint_start;
unsigned int tssr_offset = TSSR_OFFSET(offset);
unsigned int tssr_index = TSSR_INDEX(offset);
u32 reg;
@@ -299,7 +300,7 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
{
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hw_irq = irqd_to_hwirq(d);
- unsigned int offset = hw_irq - IRQC_TINT_START;
+ unsigned int offset = hw_irq - priv->info.tint_start;
unsigned int tssr_offset = TSSR_OFFSET(offset);
unsigned int tssr_index = TSSR_INDEX(offset);
u32 reg;
@@ -388,10 +389,10 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
{
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
- u32 titseln = hwirq - IRQC_TINT_START;
- u32 tssr_offset = TSSR_OFFSET(titseln);
- u8 tssr_index = TSSR_INDEX(titseln);
- u8 index, sense;
+ unsigned int titseln = hwirq - priv->info.tint_start;
+ unsigned int tssr_offset = TSSR_OFFSET(titseln);
+ unsigned int tssr_index = TSSR_INDEX(titseln);
+ unsigned int index, sense;
u32 reg, tssr;
switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -682,6 +683,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
}
static const struct rzg2l_hw_info rzg2l_hw_params = {
+ .tint_start = IRQC_IRQ_START + IRQC_IRQ_COUNT,
.num_irq = IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
};
--
2.43.0