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Wed, 25 Mar 2026 12:25:05 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v7 13/16] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro Date: Wed, 25 Mar 2026 19:24:28 +0000 Message-ID: <20260325192451.172562-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add tint_start variable in struct rzg2l_hw_info to handle this difference and drop the macro IRQC_TINT_START. While at it, update the variable type of titseln, tssr_offset, tssr_index, index, and sense to unsigned int, in rzg2l_tint_set_edge() as these variables are used only for calculation. Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * Updated the variable type of titseln, tssr_offset, tssr_index, index, and sense to unsigned int, in rzg2l_tint_set_edge() as these variables are used only for calculation. * Updated commit description. v4->v5: * Dropped the hw_irq range check involving info.tint_start v3->v4: * Updated commit description 'this differences->this difference'. * Updated tint_start variable type from u8-> unsigned int. v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 2b7a70bdcba1..e5543aea86b4 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,7 +22,6 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 -#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + unsigned int tint_start; unsigned int num_irq; }; =20 @@ -125,7 +126,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq =20 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned in= t hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); u32 reg; =20 reg =3D readl_relaxed(priv->base + TSCR); @@ -180,7 +181,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg= 2l_irqc_priv *priv, static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); } @@ -188,7 +189,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2= l_irqc_priv *priv, static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } @@ -253,7 +254,7 @@ static void rzfive_tint_endisable(struct irq_data *d, b= ool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - unsigned int offset =3D hwirq - IRQC_TINT_START; + unsigned int offset =3D hwirq - priv->info.tint_start; unsigned int tssr_offset =3D TSSR_OFFSET(offset); unsigned int tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -299,7 +300,7 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d= , bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); - unsigned int offset =3D hw_irq - IRQC_TINT_START; + unsigned int offset =3D hw_irq - priv->info.tint_start; unsigned int tssr_offset =3D TSSR_OFFSET(offset); unsigned int tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -388,10 +389,10 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - u32 titseln =3D hwirq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(titseln); - u8 tssr_index =3D TSSR_INDEX(titseln); - u8 index, sense; + unsigned int titseln =3D hwirq - priv->info.tint_start; + unsigned int tssr_offset =3D TSSR_OFFSET(titseln); + unsigned int tssr_index =3D TSSR_INDEX(titseln); + unsigned int index, sense; u32 reg, tssr; =20 switch (type & IRQ_TYPE_SENSE_MASK) { @@ -682,6 +683,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n } =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .tint_start =3D IRQC_IRQ_START + IRQC_IRQ_COUNT, .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, }; =20 --=20 2.43.0