From: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/G2L SoC family requires DMA resets to be deasserted for routing
some peripheral interrupts to the CPU. Asserting these resets after boot
would silently break interrupt delivery with no driver to restore them.
Mark the DMA resets as critical by adding them to the crit_resets table
in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and
r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and
ensuring they are deasserted during probe and resume.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v7->v8:
* No change
v6->v7:
* Updated r9a07g043_cpg_info by inserting a blank line before
.has_clk_mon_regs
* Replaced r9a07g044_critical_resets->r9a07g044_crit_resets and
r9a08g045_critical_resets->r9a08g045_crit_resets for consistency
v5->v6:
* Replaced r9a07g043_critical_resets->r9a07g043_crit_resets for
consistency
* Collected tag
v4->v5:
* No change
v4:
* Moved this patch from [1] as it is boot-dependent
[1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.renesas.com/
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++
drivers/clk/renesas/r9a08g045-cpg.c | 9 +++++++++
3 files changed, 31 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 33e9a1223c72..70944ef8c5b8 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
};
+static const unsigned int r9a07g043_crit_resets[] = {
+ R9A07G043_DMAC_ARESETN,
+ R9A07G043_DMAC_RST_ASYNC,
+};
+
#ifdef CONFIG_ARM64
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
#endif
+ /* Critical Resets */
+ .crit_resets = r9a07g043_crit_resets,
+ .num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
+
.has_clk_mon_regs = true,
};
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0dd264877b9a..2d3487203bf5 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
};
+static const unsigned int r9a07g044_crit_resets[] = {
+ R9A07G044_DMAC_ARESETN,
+ R9A07G044_DMAC_RST_ASYNC,
+};
+
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
@@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
.resets = r9a07g044_resets,
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
+ /* Critical Resets */
+ .crit_resets = r9a07g044_crit_resets,
+ .num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
+
.has_clk_mon_regs = true,
};
#endif
@@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
.resets = r9a07g044_resets,
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
+ /* Critical Resets */
+ .crit_resets = r9a07g044_crit_resets,
+ .num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
+
.has_clk_mon_regs = true,
};
#endif
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 79e7b19c7882..1232fec913eb 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
};
+static const unsigned int r9a08g045_crit_resets[] = {
+ R9A08G045_DMAC_ARESETN,
+ R9A08G045_DMAC_RST_ASYNC,
+};
+
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
};
@@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
+ /* Critical Resets */
+ .crit_resets = r9a08g045_crit_resets,
+ .num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
+
.has_clk_mon_regs = true,
};
--
2.43.0