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Tue, 24 Mar 2026 04:43:35 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v8 03/11] clk: renesas: r9a07g04{3,4}/r9a08g045-cpg: Add critical reset entries Date: Tue, 24 Mar 2026 11:43:08 +0000 Message-ID: <20260324114329.268249-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324114329.268249-1-biju.das.jz@bp.renesas.com> References: <20260324114329.268249-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L SoC family requires DMA resets to be deasserted for routing some peripheral interrupts to the CPU. Asserting these resets after boot would silently break interrupt delivery with no driver to restore them. Mark the DMA resets as critical by adding them to the crit_resets table in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and r9a08g045, preventing __rzg2l_cpg_assert() from asserting them and ensuring they are deasserted during probe and resume. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v7->v8: * No change v6->v7: * Updated r9a07g043_cpg_info by inserting a blank line before .has_clk_mon_regs * Replaced r9a07g044_critical_resets->r9a07g044_crit_resets and r9a08g045_critical_resets->r9a08g045_crit_resets for consistency v5->v6: * Replaced r9a07g043_critical_resets->r9a07g043_crit_resets for consistency * Collected tag v4->v5: * No change v4: * Moved this patch from [1] as it is boot-dependent [1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.ren= esas.com/ --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++ drivers/clk/renesas/r9a08g045-cpg.c | 9 +++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a0= 7g043-cpg.c index 33e9a1223c72..70944ef8c5b8 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; =20 +static const unsigned int r9a07g043_crit_resets[] =3D { + R9A07G043_DMAC_ARESETN, + R9A07G043_DMAC_RST_ASYNC, +}; + #ifdef CONFIG_ARM64 static const unsigned int r9a07g043_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G043_CRU_SYSCLK, @@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info =3D { .num_resets =3D R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif =20 + /* Critical Resets */ + .crit_resets =3D r9a07g043_crit_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g043_crit_resets), + .has_clk_mon_regs =3D true, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a0= 7g044-cpg.c index 0dd264877b9a..2d3487203bf5 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; =20 +static const unsigned int r9a07g044_crit_resets[] =3D { + R9A07G044_DMAC_ARESETN, + R9A07G044_DMAC_RST_ASYNC, +}; + static const unsigned int r9a07g044_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, MOD_CLK_BASE + R9A07G044_CRU_VCLK, @@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_crit_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_crit_resets), + .has_clk_mon_regs =3D true, }; #endif @@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_crit_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_crit_resets), + .has_clk_mon_regs =3D true, }; #endif diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 79e7b19c7882..1232fec913eb 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; =20 +static const unsigned int r9a08g045_crit_resets[] =3D { + R9A08G045_DMAC_ARESETN, + R9A08G045_DMAC_RST_ASYNC, +}; + static const unsigned int r9a08g045_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM, }; @@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { .resets =3D r9a08g045_resets, .num_resets =3D R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a08g045_crit_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a08g045_crit_resets), + .has_clk_mon_regs =3D true, }; --=20 2.43.0