From: Biju Das <biju.das.jz@bp.renesas.com>
Hi all,
This patch series adds initial support for the Renesas RZ/G3L SoC and
RZ/G3L SMARC EVK platform. The RZ/G3L device is a general-purpose
microprocessor with a quad-core CA-55, single core CM-33, Mali-G31
3-D Graphics and other peripherals.
Support for the below list of blocks is added in the SoC DTSI (r9a08g046.dtsi):
- EXT CLK
- 4X CA55
- SCIF
- CPG
- GIC
- ARMv8 Timer
This series also adds SCIF support for the RZ/G3L SMARC EVK board (r9a08g046l48-smarc.dts).
v5->v6:
* Collected tags
* Moved loop variable declaration inside for loops in
__rzg2l_cpg_assert() and rzg2l_cpg_deassert_crit_resets()
* Replaced r9a07g043_critical_resets[] -> r9a07g043_crit_resets[] for
consistency
* Introduced rzg2l_mod_clock_init_mstop_helper() for code reuse
in probe() and resume().
* Dropped the list implementation.
* Replaced rzg2l_mod_clock_init_mstop->rzg2l_mod_enable_crit_clock_init_mstop()
for enabling critical clks and restoring mstop state during resume.
* Dropped dma-ranges, bus-range and comment from the pcie device node
v4->v5:
* Rebased to next-20260317.
v3->v4:
* Dropped SoC identification patches as it is accepted for renesas-devel.
* Updated commit description related to core clocks section in the
hardware manual
* Dropped CLK_P4_DIV2 from core clocks
* Added MIPI_DSI_PLLCLK and USB_SCLK to core clocks
* Dropped LVDS_PCLK module clock
* Added BSC_X_PRESET_BSC reset
* Moved the patch series from [1] to here as it is boot-dependent.
* Updated commit description
* Updated LAST_DT_CORE_CLK with R9A08G046_USB_SCLK
* Fixed typo 2->8 in dtable_4_128[].
* Added critical reset table r9a08g046_critical_resets[]
* Updated num_resets
* Added crit_resets and num_crit_resets to r9a08g046_cpg_info.
* Fixed typo R0A08G046L->R9A08G046L in commit description
* Dropped R9A08G046L46 from commit description
* Dropped unused audio_clk{1,2} andcan_clk device nodes
* Reordered i2c device node and updated reg entries by using lower-case
hexadecimal number
* Added placeholder in pinctrl node
* Dropped unused DMAC device node
* Added pcie node with placeholder
* Collected the tags.
* Updated commit description for patch#8
[1] https://lore.kernel.org/all/20260306134228.871815-1-biju.das.jz@bp.renesas.com/
v2->v3:
* Added macros R9A08G046_ETH{0,1}_CLK_{TX,RX}_I_RMII in r9a08g046-cpg.h.
* Keep the tag from Conor as it is trivial change for just adding macros.
v1->v2:
* Dropped scif bindings patch as it is accepted.
* Collected tags.
* Squashed the patch#3 and #4
* Documented GE3D/VCP for all SoC variants
* Documented external ethernet clocks as it is a clock source for MUX
inside CPG
* Updated commit description for bindings.
* Keep the tag from Conor as it is trivial change for adding more
clks.
* Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks
in clk table.
* Dropped R9A08G046_IA55_PCLK from critical clock list.
* Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk
in soc dtsi as it needed for cpg as it is a clock source for mux.
* Updated cpg node.
* Dropped gpio.h header from SoM dtsi.
* Dropped scif node as it is already included in common platform
file.
Test logs:
/ # uname -r
7.0.0-rc4-next-20260317-gb478da6183c1
/ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 2
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 3
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
/ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 104 191 429 62 GICv3 27 Level arch_timer
14: 0 0 0 0 GICv3 418 Level 100ac000.serial:rx err
15: 4 0 0 0 GICv3 420 Level 100ac000.serial:rx full
16: 229 0 0 0 GICv3 421 Level 100ac000.serial:tx empty
17: 0 0 0 0 GICv3 419 Level 100ac000.serial:break
18: 17 0 0 0 GICv3 422 Level 100ac000.serial:rx ready
IPI0: 3 16 13 21 Rescheduling interrupts
IPI1: 315 240 180 217 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop NMIs
IPI4: 0 0 0 0 Timer broadcast interrupts
IPI5: 0 0 0 0 IRQ work interrupts
IPI6: 0 0 0 0 CPU backtrace interrupts
IPI7: 0 0 0 0 KGDB roundup interrupts
Err: 0
/ # cat /proc/meminfo
MemTotal: 1887304 kB
MemFree: 1852164 kB
MemAvailable: 1819524 kB
/ # cat /sys/devices/soc0/family
RZ/G3L
/ # cat /sys/devices/soc0/machine
Renesas SMARC EVK version 2 based on r9a08g046l48
/ # cat /sys/devices/soc0/soc_id
r9a08g046
/ # cat /sys/devices/soc0/revision
0
dmesg | grep r9a
[ 0.000000] Machine model: Renesas SMARC EVK version 2 based on r9a08g046l48
[ 0.066480] renesas-rz-sysc 11020000.system-controller: Detected Renesas RZ/G3L r9a08g046 Rev 0
Biju Das (10):
dt-bindings: clock: Document RZ/G3L SoC
clk: renesas: rzg2l-cpg: Add support for critical resets
clk: renesas: r9a07g04{3,4}/r9a08g045-cpg: Add critical reset entries
clk: renesas: rzg2l-cpg: Add rzg2l_mod_clock_init_mstop_helper()
clk: renesas: rzg2l-cpg: Re-enable critical module clocks during
resume
clk: renesas: Add support for RZ/G3L SoC
arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK
board
.../bindings/clock/renesas,rzg2l-cpg.yaml | 40 +-
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 212 +++++++++++
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 37 ++
arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 +
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 6 +
.../boot/dts/renesas/renesas-smarc2.dtsi | 8 -
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 20 +
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g043-cpg.c | 8 +
drivers/clk/renesas/r9a07g044-cpg.c | 13 +
drivers/clk/renesas/r9a08g045-cpg.c | 9 +
drivers/clk/renesas/r9a08g046-cpg.c | 153 ++++++++
drivers/clk/renesas/rzg2l-cpg.c | 79 +++-
drivers/clk/renesas/rzg2l-cpg.h | 8 +
include/dt-bindings/clock/r9a08g046-cpg.h | 342 ++++++++++++++++++
17 files changed, 934 insertions(+), 24 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c
create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h
--
2.43.0