From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add support for the PCIe controller found on the RZ/V2H(P) SoC. The
RZ/V2H(P) controller is similar to the RZ/G3E variant but includes
additional registers and configuration bits for PCIe lane control, and
supports multilink operation selectable between a single x4 port or two
independent x2 ports.
The RZ/V2H(P) SoC supports multilink operation, in which it provides
two independent PCIe channels (channel 0 and channel 1). To correctly
configure the multilink mode and per-channel PCIe settings in the SYS
registers, make the "linux,pci-domain" and "num-lanes" properties
mandatory for this SoC and restrict their values as per the SoC
requirements.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/pci/renesas,r9a08g045-pcie.yaml | 22 +++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
index 858ec02e6d62..57807d0abd9a 100644
--- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
@@ -14,7 +14,7 @@ description: |
with PCIe Base Specification 4.0 and supports different link speeds
depending on the SoC variant:
- Gen2 (5 GT/s): RZ/G3S
- - Gen3 (8 GT/s): RZ/G3E, RZ/V2N
+ - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N
properties:
compatible:
@@ -22,6 +22,7 @@ properties:
- enum:
- renesas,r9a08g045-pcie # RZ/G3S
- renesas,r9a09g047-pcie # RZ/G3E
+ - renesas,r9a09g057-pcie # RZ/V2H(P)
- items:
- const: renesas,r9a09g056-pcie # RZ/V2N
- const: renesas,r9a09g047-pcie
@@ -220,7 +221,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a09g047-pcie
+ enum:
+ - renesas,r9a09g047-pcie
+ - renesas,r9a09g057-pcie
then:
properties:
interrupts:
@@ -236,6 +239,21 @@ allOf:
reset-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-pcie
+ then:
+ properties:
+ linux,pci-domain:
+ enum: [0, 1]
+ num-lanes:
+ enum: [2, 4]
+ required:
+ - linux,pci-domain
+ - num-lanes
+
unevaluatedProperties: false
examples:
--
2.53.0Hi, Prabhakar, On 3/18/26 14:44, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add support for the PCIe controller found on the RZ/V2H(P) SoC. The > RZ/V2H(P) controller is similar to the RZ/G3E variant but includes > additional registers and configuration bits for PCIe lane control, and > supports multilink operation selectable between a single x4 port or two > independent x2 ports. > > The RZ/V2H(P) SoC supports multilink operation, in which it provides > two independent PCIe channels (channel 0 and channel 1). To correctly > configure the multilink mode and per-channel PCIe settings in the SYS > registers, make the "linux,pci-domain" and "num-lanes" properties > mandatory for this SoC and restrict their values as per the SoC > requirements. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../bindings/pci/renesas,r9a08g045-pcie.yaml | 22 +++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml > index 858ec02e6d62..57807d0abd9a 100644 > --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml > @@ -14,7 +14,7 @@ description: | > with PCIe Base Specification 4.0 and supports different link speeds > depending on the SoC variant: > - Gen2 (5 GT/s): RZ/G3S > - - Gen3 (8 GT/s): RZ/G3E, RZ/V2N > + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N > > properties: > compatible: > @@ -22,6 +22,7 @@ properties: > - enum: > - renesas,r9a08g045-pcie # RZ/G3S > - renesas,r9a09g047-pcie # RZ/G3E > + - renesas,r9a09g057-pcie # RZ/V2H(P) > - items: > - const: renesas,r9a09g056-pcie # RZ/V2N > - const: renesas,r9a09g047-pcie > @@ -220,7 +221,9 @@ allOf: > properties: > compatible: > contains: > - const: renesas,r9a09g047-pcie > + enum: > + - renesas,r9a09g047-pcie > + - renesas,r9a09g057-pcie > then: > properties: > interrupts: > @@ -236,6 +239,21 @@ allOf: > reset-names: > maxItems: 1 > There are empty lines b/w the above if-then conditionals. To cope with that maybe drop this one here as well. Thank you, Claudiu > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a09g057-pcie > + then: > + properties: > + linux,pci-domain: > + enum: [0, 1] > + num-lanes: > + enum: [2, 4] > + required: > + - linux,pci-domain > + - num-lanes > + > unevaluatedProperties: false > > examples:
On Wed, Mar 18, 2026 at 12:44:47PM +0000, Prabhakar wrote: > then: > properties: > interrupts: > @@ -236,6 +239,21 @@ allOf: > reset-names: > maxItems: 1 > I do not have above hunk in next from 16th March. Nothing about dependencies in cover letter or changelog. What am I missing? > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a09g057-pcie > + then: > + properties: > + linux,pci-domain: > + enum: [0, 1] > + num-lanes: > + enum: [2, 4] > + required: > + - linux,pci-domain > + - num-lanes Best regards, Krzysztof
Hi Krzysztof, On Thu, Mar 19, 2026 at 9:34 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Wed, Mar 18, 2026 at 12:44:47PM +0000, Prabhakar wrote: > > then: > > properties: > > interrupts: > > @@ -236,6 +239,21 @@ allOf: > > reset-names: > > maxItems: 1 > > > > I do not have above hunk in next from 16th March. Nothing about > dependencies in cover letter or changelog. What am I missing? > My bad, this applies on top of next-20260317. Cheers, Prabhakar
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