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Wed, 18 Mar 2026 05:45:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Claudiu Beznea , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: John Madieu , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/5] dt-bindings: pci: renesas,r9a08g045-pcie: Add RZ/V2H(P) support Date: Wed, 18 Mar 2026 12:44:47 +0000 Message-ID: <20260318124450.163471-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260318124450.163471-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the PCIe controller found on the RZ/V2H(P) SoC. The RZ/V2H(P) controller is similar to the RZ/G3E variant but includes additional registers and configuration bits for PCIe lane control, and supports multilink operation selectable between a single x4 port or two independent x2 ports. The RZ/V2H(P) SoC supports multilink operation, in which it provides two independent PCIe channels (channel 0 and channel 1). To correctly configure the multilink mode and per-channel PCIe settings in the SYS registers, make the "linux,pci-domain" and "num-lanes" properties mandatory for this SoC and restrict their values as per the SoC requirements. Signed-off-by: Lad Prabhakar --- .../bindings/pci/renesas,r9a08g045-pcie.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index 858ec02e6d62..57807d0abd9a 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -14,7 +14,7 @@ description: | with PCIe Base Specification 4.0 and supports different link speeds depending on the SoC variant: - Gen2 (5 GT/s): RZ/G3S - - Gen3 (8 GT/s): RZ/G3E, RZ/V2N + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N =20 properties: compatible: @@ -22,6 +22,7 @@ properties: - enum: - renesas,r9a08g045-pcie # RZ/G3S - renesas,r9a09g047-pcie # RZ/G3E + - renesas,r9a09g057-pcie # RZ/V2H(P) - items: - const: renesas,r9a09g056-pcie # RZ/V2N - const: renesas,r9a09g047-pcie @@ -220,7 +221,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g047-pcie + enum: + - renesas,r9a09g047-pcie + - renesas,r9a09g057-pcie then: properties: interrupts: @@ -236,6 +239,21 @@ allOf: reset-names: maxItems: 1 =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-pcie + then: + properties: + linux,pci-domain: + enum: [0, 1] + num-lanes: + enum: [2, 4] + required: + - linux,pci-domain + - num-lanes + unevaluatedProperties: false =20 examples: --=20 2.53.0