Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs.
Leave the PCIe3b nodes disabled by default, since the UEFI has the instance
disabled to avoid boot delays due to link failures.
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 586 +-----------------
.../qcom/{glymur-crd.dts => glymur-crd.dtsi} | 7 -
2 files changed, 1 insertion(+), 592 deletions(-)
copy arch/arm64/boot/dts/qcom/{glymur-crd.dts => glymur-crd.dtsi} (99%)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 877945319012..0efd9e27c82f 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -6,593 +6,9 @@
/dts-v1/;
#include "glymur.dtsi"
-#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */
-#include "pmh0101.dtsi" /* SPMI0: SID-1 */
-#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
-#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */
-#include "pmk8850.dtsi" /* SPMI0: SID-0 */
-#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
+#include "glymur-crd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
compatible = "qcom,glymur-crd", "qcom,glymur";
-
- aliases {
- serial0 = &uart21;
- serial1 = &uart14;
- i2c0 = &i2c0;
- i2c1 = &i2c4;
- i2c2 = &i2c5;
- spi0 = &spi18;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- clocks {
- xo_board: xo-board {
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- #clock-cells = <0>;
- };
-
- sleep_clk: sleep-clk {
- compatible = "fixed-clock";
- clock-frequency = <32000>;
- #clock-cells = <0>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&key_vol_up_default>;
- pinctrl-names = "default";
-
- key-volume-up {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>;
- debounce-interval = <15>;
- linux,can-disable;
- wakeup-source;
- };
- };
-
- vreg_nvme: regulator-nvme {
- compatible = "regulator-fixed";
-
- regulator-name = "VREG_NVME_3P3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-0 = <&nvme_reg_en>;
- pinctrl-names = "default";
-
- regulator-boot-on;
- };
-
- vreg_nvmesec: regulator-nvmesec {
- compatible = "regulator-fixed";
-
- regulator-name = "VREG_NVME_SEC_3P3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-0 = <&nvme_sec_reg_en>;
- pinctrl-names = "default";
-
- regulator-boot-on;
- };
-
- vreg_wlan: regulator-wlan {
- compatible = "regulator-fixed";
-
- regulator-name = "VREG_WLAN_3P3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-0 = <&wlan_reg_en>;
- pinctrl-names = "default";
-
- regulator-boot-on;
- };
-
- vreg_wwan: regulator-wwan {
- compatible = "regulator-fixed";
-
- regulator-name = "VREG_WWAN_3P3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-0 = <&wwan_reg_en>;
- pinctrl-names = "default";
- };
-};
-
-&apps_rsc {
- regulators-0 {
- compatible = "qcom,pmh0101-rpmh-regulators";
- qcom,pmic-id = "B_E0";
-
- vreg_bob1_e0: bob1 {
- regulator-name = "vreg_bob1_e0";
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <4224000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
- };
-
- vreg_bob2_e0: bob2 {
- regulator-name = "vreg_bob2_e0";
- regulator-min-microvolt = <2540000>;
- regulator-max-microvolt = <3600000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
- };
-
- vreg_l1b_e0_1p8: ldo1 {
- regulator-name = "vreg_l1b_e0_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2b_e0_2p9: ldo2 {
- regulator-name = "vreg_l2b_e0_2p9";
- regulator-min-microvolt = <2904000>;
- regulator-max-microvolt = <2904000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l7b_e0_2p79: ldo7 {
- regulator-name = "vreg_l7b_e0_2p79";
- regulator-min-microvolt = <2790000>;
- regulator-max-microvolt = <2792000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l8b_e0_1p50: ldo8 {
- regulator-name = "vreg_l8b_e0_1p50";
- regulator-min-microvolt = <1504000>;
- regulator-max-microvolt = <1504000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9b_e0_2p7: ldo9 {
- regulator-name = "vreg_l9b_e0_2p7";
- regulator-min-microvolt = <2704000>;
- regulator-max-microvolt = <2704000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l10b_e0_1p8: ldo10 {
- regulator-name = "vreg_l10b_e0_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l11b_e0_1p2: ldo11 {
- regulator-name = "vreg_l11b_e0_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l12b_e0_1p14: ldo12 {
- regulator-name = "vreg_l12b_e0_1p14";
- regulator-min-microvolt = <1144000>;
- regulator-max-microvolt = <1144000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l15b_e0_1p8: ldo15 {
- regulator-name = "vreg_l15b_e0_1p8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l17b_e0_2p4: ldo17 {
- regulator-name = "vreg_l17b_e0_2p4";
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <2700000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l18b_e0_1p2: ldo18 {
- regulator-name = "vreg_l18b_e0_1p2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-1 {
- compatible = "qcom,pmcx0102-rpmh-regulators";
- qcom,pmic-id = "C_E1";
-
- vreg_l1c_e1_0p82: ldo1 {
- regulator-name = "vreg_l1c_e1_0p82";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2c_e1_1p14: ldo2 {
- regulator-name = "vreg_l2c_e1_1p14";
- regulator-min-microvolt = <1144000>;
- regulator-max-microvolt = <1144000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l3c_e1_0p89: ldo3 {
- regulator-name = "vreg_l3c_e1_0p89";
- regulator-min-microvolt = <890000>;
- regulator-max-microvolt = <980000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4c_e1_0p72: ldo4 {
- regulator-name = "vreg_l4c_e1_0p72";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <720000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-2 {
- compatible = "qcom,pmh0110-rpmh-regulators";
- qcom,pmic-id = "F_E0";
-
- vreg_s7f_e0_1p32: smps7 {
- regulator-name = "vreg_s7f_e0_1p32";
- regulator-min-microvolt = <1320000>;
- regulator-max-microvolt = <1352000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s8f_e0_0p95: smps8 {
- regulator-name = "vreg_s8f_e0_0p95";
- regulator-min-microvolt = <952000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s9f_e0_1p9: smps9 {
- regulator-name = "vreg_s9f_e0_1p9";
- regulator-min-microvolt = <1900000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2f_e0_0p82: ldo2 {
- regulator-name = "vreg_l2f_e0_0p82";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l3f_e0_0p72: ldo3 {
- regulator-name = "vreg_l3f_e0_0p72";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <720000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4f_e0_0p3: ldo4 {
- regulator-name = "vreg_l4f_e0_0p3";
- regulator-min-microvolt = <1080000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-3 {
- compatible = "qcom,pmh0110-rpmh-regulators";
- qcom,pmic-id = "F_E1";
-
- vreg_s7f_e1_0p3: smps7 {
- regulator-name = "vreg_s7f_e1_0p3";
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l1f_e1_0p82: ldo1 {
- regulator-name = "vreg_l1f_e1_0p82";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2f_e1_0p83: ldo2 {
- regulator-name = "vreg_l2f_e1_0p83";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4f_e1_1p08: ldo4 {
- regulator-name = "vreg_l4f_e1_1p08";
- regulator-min-microvolt = <1080000>;
- regulator-max-microvolt = <1320000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-4 {
- compatible = "qcom,pmh0110-rpmh-regulators";
- qcom,pmic-id = "H_E0";
-
- vreg_l1h_e0_0p89: ldo1 {
- regulator-name = "vreg_l1h_e0_0p89";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2h_e0_0p72: ldo2 {
- regulator-name = "vreg_l2h_e0_0p72";
- regulator-min-microvolt = <832000>;
- regulator-max-microvolt = <832000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l3h_e0_0p32: ldo3 {
- regulator-name = "vreg_l3h_e0_0p32";
- regulator-min-microvolt = <320000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4h_e0_1p2: ldo4 {
- regulator-name = "vreg_l4h_e0_1p2";
- regulator-min-microvolt = <1080000>;
- regulator-max-microvolt = <1320000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-};
-
-&pcie3b {
- vddpe-3v3-supply = <&vreg_nvmesec>;
-
- pinctrl-0 = <&pcie3b_default>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie3b_phy {
- vdda-phy-supply = <&vreg_l3c_e1_0p89>;
- vdda-pll-supply = <&vreg_l2c_e1_1p14>;
-
- status = "okay";
-};
-
-&pcie3b_port0 {
- reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>;
-};
-
-&pcie4 {
- vddpe-3v3-supply = <&vreg_wlan>;
-
- pinctrl-0 = <&pcie4_default>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie4_phy {
- vdda-phy-supply = <&vreg_l1c_e1_0p82>;
- vdda-pll-supply = <&vreg_l4f_e1_1p08>;
-
- status = "okay";
-};
-
-&pcie4_port0 {
- reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-};
-
-&pcie5 {
- vddpe-3v3-supply = <&vreg_nvme>;
-
- pinctrl-0 = <&pcie5_default>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie5_phy {
- vdda-phy-supply = <&vreg_l2f_e0_0p82>;
- vdda-pll-supply = <&vreg_l4h_e0_1p2>;
-
- status = "okay";
-};
-
-&pcie5_port0 {
- reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-};
-
-&pcie6 {
- vddpe-3v3-supply = <&vreg_wwan>;
-
- pinctrl-0 = <&pcie6_default>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pcie6_phy {
- vdda-phy-supply = <&vreg_l1c_e1_0p82>;
- vdda-pll-supply = <&vreg_l4f_e1_1p08>;
-
- status = "okay";
-};
-
-&pcie6_port0 {
- reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
-};
-
-&pmh0101_gpios {
- nvme_reg_en: nvme-reg-en-state {
- pins = "gpio14";
- function = "normal";
- bias-disable;
- };
-};
-
-&pmh0110_f_e1_gpios {
- nvme_sec_reg_en: nvme-reg-en-state {
- pins = "gpio14";
- function = "normal";
- bias-disable;
- };
-};
-
-&pmh0101_gpios {
- key_vol_up_default: key-vol-up-default-state {
- pins = "gpio6";
- function = "normal";
- output-disable;
- bias-pull-up;
- };
-};
-
-&pmk8850_rtc {
- qcom,no-alarm;
-};
-
-&pon_resin {
- linux,code = <KEY_VOLUMEDOWN>;
- status = "okay";
-};
-
-&tlmm {
- gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
- <10 2>, /* OOB UART */
- <44 4>; /* Security SPI (TPM) */
-
- pcie4_default: pcie4-default-state {
- clkreq-n-pins {
- pins = "gpio147";
- function = "pcie4_clk_req_n";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- perst-n-pins {
- pins = "gpio146";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- wake-n-pins {
- pins = "gpio148";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie5_default: pcie5-default-state {
- clkreq-n-pins {
- pins = "gpio153";
- function = "pcie5_clk_req_n";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- perst-n-pins {
- pins = "gpio152";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- wake-n-pins {
- pins = "gpio154";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie6_default: pcie6-default-state {
- clkreq-n-pins {
- pins = "gpio150";
- function = "pcie6_clk_req_n";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- perst-n-pins {
- pins = "gpio149";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- wake-n-pins {
- pins = "gpio151";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie3b_default: pcie3b-default-state {
- clkreq-n-pins {
- pins = "gpio156";
- function = "pcie3b_clk";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- perst-n-pins {
- pins = "gpio155";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- wake-n-pins {
- pins = "gpio157";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- wlan_reg_en: wlan-reg-en-state {
- pins = "gpio94";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- wwan_reg_en: wwan-reg-en-state {
- pins = "gpio246";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
};
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
similarity index 99%
copy from arch/arm64/boot/dts/qcom/glymur-crd.dts
copy to arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index 877945319012..abc6cc8bb0a8 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -3,9 +3,6 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
-/dts-v1/;
-
-#include "glymur.dtsi"
#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */
#include "pmh0101.dtsi" /* SPMI0: SID-1 */
#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
@@ -372,15 +369,11 @@ &pcie3b {
pinctrl-0 = <&pcie3b_default>;
pinctrl-names = "default";
-
- status = "okay";
};
&pcie3b_phy {
vdda-phy-supply = <&vreg_l3c_e1_0p89>;
vdda-pll-supply = <&vreg_l2c_e1_1p14>;
-
- status = "okay";
};
&pcie3b_port0 {
--
2.34.1On Wed, Mar 18, 2026 at 05:40:59AM -0700, Gopikrishna Garmidi wrote:
> Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs.
>
> Leave the PCIe3b nodes disabled by default, since the UEFI has the instance
> disabled to avoid boot delays due to link failures.
>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 586 +-----------------
> .../qcom/{glymur-crd.dts => glymur-crd.dtsi} | 7 -
> 2 files changed, 1 insertion(+), 592 deletions(-)
> copy arch/arm64/boot/dts/qcom/{glymur-crd.dts => glymur-crd.dtsi} (99%)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
© 2016 - 2026 Red Hat, Inc.