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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c0e53b5fa1sm4454521eec.10.2026.03.18.05.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 05:41:17 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Gopikrishna Garmidi Subject: [PATCH v2 2/3] arm64: dts: qcom: Commonize Glymur CRD DTSI Date: Wed, 18 Mar 2026 05:40:59 -0700 Message-Id: <20260318124100.212992-3-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260318124100.212992-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 9UkgEqVAOYWzK6XJ1eQYwHbvW_JZlV3o X-Proofpoint-GUID: 9UkgEqVAOYWzK6XJ1eQYwHbvW_JZlV3o X-Authority-Analysis: v=2.4 cv=U4ifzOru c=1 sm=1 tr=0 ts=69ba9d6f cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Lx9aQ9xY3w96JebXmp4A:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDEwOCBTYWx0ZWRfXwqNiV0kYIsmN +6YMEo7YCjg/ywxxH3+N5PBpm+mTAXyVCHxhQMy7AYJa69uAohm0CA0EA0NWlRdh8OgiX4MVrNX ZRI4UJq3KhonJRhgkVuiLo+ubuaxQcxtBaYorm5tTboWpTMykKMJN6Mj4xorKuSfpuIouVnq+Sj N5gGi6AEBn0CR+P4uGB+0rvw7y0uJlgPtBC9Tx63qLBovpY3doT0DmSGaz9epUzyBIDWbQ9xYUZ TlOfZwUnQwoDu605IQ6DDkeccHE23vW+/rmYpYQiNLOY+XxGb68doikPLXoFfCI2bTt/ySWPGoU upi5+p4sH+lNpVw6YDm2DfppXV4+T/MYVuiuT4X9fCTn7hJbEafUfsnPlRlltlM2YgyUqyrUsQI WJQtBFSDN8DhNmJs+HPViKAovoYklBhyfZ1Ut9TPyShenT8faD63GrZh+QGzZ78mfvfgfsX00K5 wYNgIQBN8awMnfjND9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-18_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180108 Content-Type: text/plain; charset="utf-8" Commonize the existing Glymur CRD DTSI to allow reuse with Mahua CRDs. Leave the PCIe3b nodes disabled by default, since the UEFI has the instance disabled to avoid boot delays due to link failures. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 586 +----------------- .../qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} | 7 - 2 files changed, 1 insertion(+), 592 deletions(-) copy arch/arm64/boot/dts/qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 877945319012..0efd9e27c82f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -6,593 +6,9 @@ /dts-v1/; =20 #include "glymur.dtsi" -#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ -#include "pmh0101.dtsi" /* SPMI0: SID-1 */ -#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ -#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ -#include "pmk8850.dtsi" /* SPMI0: SID-0 */ -#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include "glymur-crd.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. Glymur CRD"; compatible =3D "qcom,glymur-crd", "qcom,glymur"; - - aliases { - serial0 =3D &uart21; - serial1 =3D &uart14; - i2c0 =3D &i2c0; - i2c1 =3D &i2c4; - i2c2 =3D &i2c5; - spi0 =3D &spi18; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - clocks { - xo_board: xo-board { - compatible =3D "fixed-clock"; - clock-frequency =3D <38400000>; - #clock-cells =3D <0>; - }; - - sleep_clk: sleep-clk { - compatible =3D "fixed-clock"; - clock-frequency =3D <32000>; - #clock-cells =3D <0>; - }; - }; - - gpio-keys { - compatible =3D "gpio-keys"; - - pinctrl-0 =3D <&key_vol_up_default>; - pinctrl-names =3D "default"; - - key-volume-up { - label =3D "Volume Up"; - linux,code =3D ; - gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval =3D <15>; - linux,can-disable; - wakeup-source; - }; - }; - - vreg_nvme: regulator-nvme { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_nvmesec: regulator-nvmesec { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_SEC_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_sec_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wlan: regulator-wlan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WLAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wlan_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WWAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wwan_reg_en>; - pinctrl-names =3D "default"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible =3D "qcom,pmh0101-rpmh-regulators"; - qcom,pmic-id =3D "B_E0"; - - vreg_bob1_e0: bob1 { - regulator-name =3D "vreg_bob1_e0"; - regulator-min-microvolt =3D <2200000>; - regulator-max-microvolt =3D <4224000>; - regulator-initial-mode =3D ; - }; - - vreg_bob2_e0: bob2 { - regulator-name =3D "vreg_bob2_e0"; - regulator-min-microvolt =3D <2540000>; - regulator-max-microvolt =3D <3600000>; - regulator-initial-mode =3D ; - }; - - vreg_l1b_e0_1p8: ldo1 { - regulator-name =3D "vreg_l1b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l2b_e0_2p9: ldo2 { - regulator-name =3D "vreg_l2b_e0_2p9"; - regulator-min-microvolt =3D <2904000>; - regulator-max-microvolt =3D <2904000>; - regulator-initial-mode =3D ; - }; - - vreg_l7b_e0_2p79: ldo7 { - regulator-name =3D "vreg_l7b_e0_2p79"; - regulator-min-microvolt =3D <2790000>; - regulator-max-microvolt =3D <2792000>; - regulator-initial-mode =3D ; - }; - - vreg_l8b_e0_1p50: ldo8 { - regulator-name =3D "vreg_l8b_e0_1p50"; - regulator-min-microvolt =3D <1504000>; - regulator-max-microvolt =3D <1504000>; - regulator-initial-mode =3D ; - }; - - vreg_l9b_e0_2p7: ldo9 { - regulator-name =3D "vreg_l9b_e0_2p7"; - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2704000>; - regulator-initial-mode =3D ; - }; - - vreg_l10b_e0_1p8: ldo10 { - regulator-name =3D "vreg_l10b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l11b_e0_1p2: ldo11 { - regulator-name =3D "vreg_l11b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l12b_e0_1p14: ldo12 { - regulator-name =3D "vreg_l12b_e0_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l15b_e0_1p8: ldo15 { - regulator-name =3D "vreg_l15b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l17b_e0_2p4: ldo17 { - regulator-name =3D "vreg_l17b_e0_2p4"; - regulator-min-microvolt =3D <2400000>; - regulator-max-microvolt =3D <2700000>; - regulator-initial-mode =3D ; - }; - - vreg_l18b_e0_1p2: ldo18 { - regulator-name =3D "vreg_l18b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-1 { - compatible =3D "qcom,pmcx0102-rpmh-regulators"; - qcom,pmic-id =3D "C_E1"; - - vreg_l1c_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1c_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2c_e1_1p14: ldo2 { - regulator-name =3D "vreg_l2c_e1_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l3c_e1_0p89: ldo3 { - regulator-name =3D "vreg_l3c_e1_0p89"; - regulator-min-microvolt =3D <890000>; - regulator-max-microvolt =3D <980000>; - regulator-initial-mode =3D ; - }; - - vreg_l4c_e1_0p72: ldo4 { - regulator-name =3D "vreg_l4c_e1_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-2 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E0"; - - vreg_s7f_e0_1p32: smps7 { - regulator-name =3D "vreg_s7f_e0_1p32"; - regulator-min-microvolt =3D <1320000>; - regulator-max-microvolt =3D <1352000>; - regulator-initial-mode =3D ; - }; - - vreg_s8f_e0_0p95: smps8 { - regulator-name =3D "vreg_s8f_e0_0p95"; - regulator-min-microvolt =3D <952000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_s9f_e0_1p9: smps9 { - regulator-name =3D "vreg_s9f_e0_1p9"; - regulator-min-microvolt =3D <1900000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e0_0p82: ldo2 { - regulator-name =3D "vreg_l2f_e0_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3f_e0_0p72: ldo3 { - regulator-name =3D "vreg_l3f_e0_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e0_0p3: ldo4 { - regulator-name =3D "vreg_l4f_e0_0p3"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-3 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E1"; - - vreg_s7f_e1_0p3: smps7 { - regulator-name =3D "vreg_s7f_e1_0p3"; - regulator-min-microvolt =3D <300000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l1f_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1f_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e1_0p83: ldo2 { - regulator-name =3D "vreg_l2f_e1_0p83"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e1_1p08: ldo4 { - regulator-name =3D "vreg_l4f_e1_1p08"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-4 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "H_E0"; - - vreg_l1h_e0_0p89: ldo1 { - regulator-name =3D "vreg_l1h_e0_0p89"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2h_e0_0p72: ldo2 { - regulator-name =3D "vreg_l2h_e0_0p72"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3h_e0_0p32: ldo3 { - regulator-name =3D "vreg_l3h_e0_0p32"; - regulator-min-microvolt =3D <320000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l4h_e0_1p2: ldo4 { - regulator-name =3D "vreg_l4h_e0_1p2"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; -}; - -&pcie3b { - vddpe-3v3-supply =3D <&vreg_nvmesec>; - - pinctrl-0 =3D <&pcie3b_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie3b_phy { - vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; - vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; - - status =3D "okay"; -}; - -&pcie3b_port0 { - reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; -}; - -&pcie4 { - vddpe-3v3-supply =3D <&vreg_wlan>; - - pinctrl-0 =3D <&pcie4_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie4_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie4_port0 { - reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; -}; - -&pcie5 { - vddpe-3v3-supply =3D <&vreg_nvme>; - - pinctrl-0 =3D <&pcie5_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie5_phy { - vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; - vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; - - status =3D "okay"; -}; - -&pcie5_port0 { - reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pcie6 { - vddpe-3v3-supply =3D <&vreg_wwan>; - - pinctrl-0 =3D <&pcie6_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie6_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie6_port0 { - reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; -}; - -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0110_f_e1_gpios { - nvme_sec_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0101_gpios { - key_vol_up_default: key-vol-up-default-state { - pins =3D "gpio6"; - function =3D "normal"; - output-disable; - bias-pull-up; - }; -}; - -&pmk8850_rtc { - qcom,no-alarm; -}; - -&pon_resin { - linux,code =3D ; - status =3D "okay"; -}; - -&tlmm { - gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ - <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins =3D "gpio147"; - function =3D "pcie4_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio146"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio148"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins =3D "gpio153"; - function =3D "pcie5_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio152"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio154"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie6_default: pcie6-default-state { - clkreq-n-pins { - pins =3D "gpio150"; - function =3D "pcie6_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio149"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio151"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie3b_default: pcie3b-default-state { - clkreq-n-pins { - pins =3D "gpio156"; - function =3D "pcie3b_clk"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio155"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio157"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - wlan_reg_en: wlan-reg-en-state { - pins =3D "gpio94"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wwan_reg_en: wwan-reg-en-state { - pins =3D "gpio246"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dtsi similarity index 99% copy from arch/arm64/boot/dts/qcom/glymur-crd.dts copy to arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 877945319012..abc6cc8bb0a8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -3,9 +3,6 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 -/dts-v1/; - -#include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ #include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ @@ -372,15 +369,11 @@ &pcie3b { =20 pinctrl-0 =3D <&pcie3b_default>; pinctrl-names =3D "default"; - - status =3D "okay"; }; =20 &pcie3b_phy { vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; - - status =3D "okay"; }; =20 &pcie3b_port0 { --=20 2.34.1