[v2] Add devicetree nodes for RK3528, RK3562 and RK356x

[PATCH v2 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x

Posted by Heiko Stuebner 2 weeks, 6 days ago

Enable the One Time Programmable Controller (OTPC) in RK356x and add
an initial nvmem fixed layout.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 68b48606f601..c8321af7de7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -1123,6 +1123,52 @@ rng: rng@fe388000 {
 		status = "disabled";
 	};
 
+	otp: efuse@fe38c000 {
+		compatible = "rockchip,rk3568-otp";
+		reg = <0x0 0xfe38c000 0x0 0x4000>;
+		clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
+			 <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
+		clock-names = "otp", "apb_pclk", "phy", "sbpi";
+		resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
+			 <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
+		reset-names = "otp", "apb", "phy", "sbpi";
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpu_code: cpu-code@2 {
+				reg = <0x02 0x2>;
+			};
+
+			otp_cpu_version: cpu-version@8 {
+				reg = <0x08 0x1>;
+				bits = <3 3>;
+			};
+
+			otp_id: id@a {
+				reg = <0x0a 0x10>;
+			};
+
+			cpu_leakage: cpu-leakage@1a {
+				reg = <0x1a 0x1>;
+			};
+
+			log_leakage: log-leakage@1b {
+				reg = <0x1b 0x1>;
+			};
+
+			npu_leakage: npu-leakage@1c {
+				reg = <0x1c 0x1>;
+			};
+
+			gpu_leakage: gpu-leakage@1d {
+				reg = <0x1d 0x1>;
+			};
+		};
+	};
+
 	i2s0_8ch: i2s@fe400000 {
 		compatible = "rockchip,rk3568-i2s-tdm";
 		reg = <0x0 0xfe400000 0x0 0x1000>;
-- 
2.47.3

Re: [PATCH v2 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x

Posted by Diederik de Haas 2 weeks, 2 days ago

Hi Heiko,

On Thu Mar 12, 2026 at 10:30 PM CET, Heiko Stuebner wrote:
> Enable the One Time Programmable Controller (OTPC) in RK356x and add
> an initial nvmem fixed layout.

I build a kernel with the nvmem patches and your patches from this
series and tried it out on my NanoPi R5S with a RK3568 SoC.
Navigating to ``/sys/bus/nvmem/devices/rockchip-otp0/cells`` and then
doing ``hexdump <cell-name>`` showed all kind of values.

Then I did the same with my PineNote with a RK3566 SoC and that gave
different values, except for npu-leakage, which I guess is fine.
So feel free to include my

Tested-by: Diederik de Haas <diederik@cknow-tech.com>  # NanoPi R5S, PineNote

Cheers,
  Diederik

> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> index 68b48606f601..c8321af7de7d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> @@ -1123,6 +1123,52 @@ rng: rng@fe388000 {
>  		status = "disabled";
>  	};
>  
> +	otp: efuse@fe38c000 {
> +		compatible = "rockchip,rk3568-otp";
> +		reg = <0x0 0xfe38c000 0x0 0x4000>;
> +		clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
> +			 <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
> +		clock-names = "otp", "apb_pclk", "phy", "sbpi";
> +		resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
> +			 <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
> +		reset-names = "otp", "apb", "phy", "sbpi";
> +
> +		nvmem-layout {
> +			compatible = "fixed-layout";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			cpu_code: cpu-code@2 {
> +				reg = <0x02 0x2>;
> +			};
> +
> +			otp_cpu_version: cpu-version@8 {
> +				reg = <0x08 0x1>;
> +				bits = <3 3>;
> +			};
> +
> +			otp_id: id@a {
> +				reg = <0x0a 0x10>;
> +			};
> +
> +			cpu_leakage: cpu-leakage@1a {
> +				reg = <0x1a 0x1>;
> +			};
> +
> +			log_leakage: log-leakage@1b {
> +				reg = <0x1b 0x1>;
> +			};
> +
> +			npu_leakage: npu-leakage@1c {
> +				reg = <0x1c 0x1>;
> +			};
> +
> +			gpu_leakage: gpu-leakage@1d {
> +				reg = <0x1d 0x1>;
> +			};
> +		};
> +	};
> +
>  	i2s0_8ch: i2s@fe400000 {
>  		compatible = "rockchip,rk3568-i2s-tdm";
>  		reg = <0x0 0xfe400000 0x0 0x1000>;

Re: [PATCH v2 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x

Posted by Diederik de Haas 2 weeks, 2 days ago

Hi Heiko,

On Thu Mar 12, 2026 at 10:30 PM CET, Heiko Stuebner wrote:
> Enable the One Time Programmable Controller (OTPC) in RK356x and add
> an initial nvmem fixed layout.

I build a kernel with the nvmem patches and your patches from this
series and tried it out on my NanoPi R5S with a RK3568 SoC.
Navigating to ``/sys/bus/nvmem/devices/rockchip-otp0/cells`` and then
doing ``hexdump <cell-name>`` showed all kind of values.

Then I did the same with my PineNote with a RK3566 SoC and that gave
different values, except for npu-leakage, which I guess is fine?
So feel free to include my

Tested-by: Diederik de Haas <diederik@cknow-tech.com>  # NanoPi R5S, PineNote

Cheers,
  Diederik

> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> index 68b48606f601..c8321af7de7d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> @@ -1123,6 +1123,52 @@ rng: rng@fe388000 {
>  		status = "disabled";
>  	};
>  
> +	otp: efuse@fe38c000 {
> +		compatible = "rockchip,rk3568-otp";
> +		reg = <0x0 0xfe38c000 0x0 0x4000>;
> +		clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
> +			 <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
> +		clock-names = "otp", "apb_pclk", "phy", "sbpi";
> +		resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
> +			 <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
> +		reset-names = "otp", "apb", "phy", "sbpi";
> +
> +		nvmem-layout {
> +			compatible = "fixed-layout";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			cpu_code: cpu-code@2 {
> +				reg = <0x02 0x2>;
> +			};
> +
> +			otp_cpu_version: cpu-version@8 {
> +				reg = <0x08 0x1>;
> +				bits = <3 3>;
> +			};
> +
> +			otp_id: id@a {
> +				reg = <0x0a 0x10>;
> +			};
> +
> +			cpu_leakage: cpu-leakage@1a {
> +				reg = <0x1a 0x1>;
> +			};
> +
> +			log_leakage: log-leakage@1b {
> +				reg = <0x1b 0x1>;
> +			};
> +
> +			npu_leakage: npu-leakage@1c {
> +				reg = <0x1c 0x1>;
> +			};
> +
> +			gpu_leakage: gpu-leakage@1d {
> +				reg = <0x1d 0x1>;
> +			};
> +		};
> +	};
> +
>  	i2s0_8ch: i2s@fe400000 {
>  		compatible = "rockchip,rk3568-i2s-tdm";
>  		reg = <0x0 0xfe400000 0x0 0x1000>;