From nobody Thu Apr 2 01:46:33 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAA9938C411 for ; Thu, 12 Mar 2026 21:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351039; cv=none; b=PpbjQjHX/jtn8INOlcZLygeMb3UywJeZPeuCkfJDRv1eJUB2cY79i1FaqzrF1sP8cRj2/xo8jTS1TLCA3xZxTyxkw0RMcF4bk9W1r9Kj5Td/wa0yFrFJ3a/IHmLI+bKGutRqM1dxhdaNQhBKt3y6Q1jLsyxNMsg7DvR1pVlS8cE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773351039; c=relaxed/simple; bh=KgFIkAfs1GLXZC0P/NOBgs+VsFokdnRyg8ICGtiBFB8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kmc7BhpM51ncwrIyofsppsraRr5fNadSJzHn8SxmBOp2RZ09KzPC1XyH1GoVZrfEJMzX7HonL4Fe8abZFSGpZMLRxsIGzHA4glRayRa2hC35YvaLOIkxuTRPqdZL08/gJQUYaFir4nEVIowDfus53UiBUb0rIwnidN+RWrIKIsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=RM48uL0K; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="RM48uL0K" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=QnKpV5HENvc+AyhAXA4SEjE+pZWBIukJfE82CHrZr5s=; b=RM48uL0K3EVMGFP7B4DRRJC9HE 9AWaD579Z2W9zuoObuxZKNstwbMefGdhXyi859koYAfuujkERVOq6EPjC0nOEdm/uNO9SXUXS7cCH NT9cknZSROgcKopcx/oPc+9EdiapZ/6nxY8f5p07KIMhMe2FHm/tfC1+zFqZXKShHbgNYS3EIwQji laVXQUZlqfz+SpEngD0GRc9bjLMKIfzgDD2kgpQe6c7WmY4dDBTfeWbC2+hlcDBxujKU5/18xj0JY HY5WWJIYcd89X69X++1Tor96Gp8NCJ8hoCVA4fj48o2lSb1XPM72UZNeVPE2oeRAjNdw3ef4PiVn1 3yIi+Vfw==; From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH v2 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x Date: Thu, 12 Mar 2026 22:30:18 +0100 Message-ID: <20260312213019.13965-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260312213019.13965-1-heiko@sntech.de> References: <20260312213019.13965-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the One Time Programmable Controller (OTPC) in RK356x and add an initial nvmem fixed layout. Signed-off-by: Heiko Stuebner Tested-by: Diederik de Haas # NanoPi R5S, PineNo= te --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 68b48606f601..c8321af7de7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1123,6 +1123,52 @@ rng: rng@fe388000 { status =3D "disabled"; }; =20 + otp: efuse@fe38c000 { + compatible =3D "rockchip,rk3568-otp"; + reg =3D <0x0 0xfe38c000 0x0 0x4000>; + clocks =3D <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; + clock-names =3D "otp", "apb_pclk", "phy", "sbpi"; + resets =3D <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; + reset-names =3D "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg =3D <0x1d 0x1>; + }; + }; + }; + i2s0_8ch: i2s@fe400000 { compatible =3D "rockchip,rk3568-i2s-tdm"; reg =3D <0x0 0xfe400000 0x0 0x1000>; --=20 2.47.3