Hi,
On 12.03.2026 12:12, Val Packett wrote:
> Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent
> clocks are enabled during clock operations, preventing potential
> stability issues during display configuration.
>
> Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
> Signed-off-by: Val Packett <val@packett.cool>
This patch landed in yesterday's linux-next as commit. In my tests I
found that it triggers the following warning on RB5 board:
------------[ cut here ]------------
dsi0_phy_pll_out_dsiclk already disabled
WARNING: drivers/clk/clk.c:1188 at clk_core_disable+0x1ac/0x1bc, CPU#1:
kworker/u32:6/120
Modules linked in: ...
CPU: 1 UID: 0 PID: 120 Comm: kworker/u32:6 Not tainted 7.0.0-rc1+ #12425
PREEMPT
Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT)
Workqueue: events_unbound deferred_probe_work_func
pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : clk_core_disable+0x1ac/0x1bc
lr : clk_core_disable+0x1ac/0x1bc
sp : ffff800081a2b990
...
Call trace:
clk_core_disable+0x1ac/0x1bc (P)
__clk_set_parent_after+0x9c/0xf0
clk_core_set_parent_nolock+0x1f8/0x230
clk_set_parent+0x40/0x84
of_clk_set_defaults+0x130/0x4b8
platform_probe+0x38/0xac
really_probe+0xbc/0x298
__driver_probe_device+0x78/0x12c
driver_probe_device+0x40/0x164
__device_attach_driver+0xa4/0x148
bus_for_each_drv+0x80/0xdc
__device_attach+0xa8/0x1b0
device_initial_probe+0x50/0x54
bus_probe_device+0x38/0xa8
deferred_probe_work_func+0x8c/0xc8
process_one_work+0x20c/0x78c
worker_thread+0x244/0x388
kthread+0x140/0x14c
ret_from_fork+0x10/0x20
irq event stamp: 336832
hardirqs last enabled at (336831): [<ffffad391268b854>]
_raw_spin_unlock_irqrestore+0x74/0x78
hardirqs last disabled at (336832): [<ffffad3911b6d8b4>]
clk_enable_lock+0xcc/0x110
softirqs last enabled at (336804): [<ffffad391134b884>]
handle_softirqs+0x624/0x63c
softirqs last disabled at (336793): [<ffffad3911290674>]
__do_softirq+0x14/0x20
---[ end trace 0000000000000000 ]---
------------[ cut here ]------------
dsi0_phy_pll_out_dsiclk already unprepared
WARNING: drivers/clk/clk.c:1047 at clk_core_unprepare+0x1f0/0x210,
CPU#6: kworker/u32:6/120
It looks like a bug in the code performing the default clocks
configuration though.
> ---
> drivers/clk/qcom/dispcc-sm8250.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
> index cdfdb2cfb02b..e59cdadd5647 100644
> --- a/drivers/clk/qcom/dispcc-sm8250.c
> +++ b/drivers/clk/qcom/dispcc-sm8250.c
> @@ -578,7 +578,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
> .name = "disp_cc_mdss_pclk0_clk_src",
> .parent_data = disp_cc_parent_data_6,
> .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
> - .flags = CLK_SET_RATE_PARENT,
> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> .ops = &clk_pixel_ops,
> },
> };
> @@ -592,7 +592,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
> .name = "disp_cc_mdss_pclk1_clk_src",
> .parent_data = disp_cc_parent_data_6,
> .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
> - .flags = CLK_SET_RATE_PARENT,
> + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> .ops = &clk_pixel_ops,
> },
> };
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland