From nobody Tue Apr 7 18:20:45 2026 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54FEE3BF674 for ; Thu, 12 Mar 2026 11:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314678; cv=none; b=oy+iUcPgGyO0UMdW7BXwcg47x0m4FIsIBEtAtFMBN+fVQ+0yJGKZvUim7v0tsVxPOUs5J0Qrg9jpBaJ2kv8MWey0H8Zxry99jR352fNf/ydVN22SIJsTWK74uSNOSnO32ijIHSUuzoPA1Edw2YmlC7cJmEJzduhi52p+4Lmx/mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314678; c=relaxed/simple; bh=uYs3JHAd/jxTQEVzpORrcnhgntV0JK5nGBynUCea0wM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GkvibpBXF4ebPzENdYqZCNmV9rNF2g+qh1ObACp1iDSpjwmV8e8qp1lH1N/pjGqK68ZcOWcrn/LwBWBfWJOiecyU3ETCWuCa+zMhK5fuyRW/JJUCWsGCV1URBuVsXrNtbh1MkuvRy7/VF/J7aQhYxdUlIu/EaCf6HzV07BF7IEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=QOqc7FP7; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="QOqc7FP7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c6bg3vbkQkQwI35FQJs6xm3Hr9kxqB+NBTc/GQ3vahI=; b=QOqc7FP7egtUy4YxR8zfb3602SOEEB9rhWA/QnV+2f5JaKXfW1kyJE8VTartiIybviRMdL eIfihcVwp2HsuMfqgetT4XofMWV0mr8sHWPW+su/TkpNUKwZbgkraCBN32xpkSfOYpTPQe e+dPBsGYka3cZ5r1M3jXy+YD9JluGTvMUqg4kItug+w4kH2rwal9luVaeGejllx/0Z+EMH 8rsnyP3xZ+e+26zbDtJ7/n+GWTS2LN3trI1BC2KWTPT5PJN2HG1nyI9JQoYkPh9CH7nhL9 Q3PDS2HCIA6LH3e6fUvh0SELS6WFLem1VFYehe/lVds7PUFqhw1JAzMErDZi8w== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/11] clk: qcom: dispcc-sm8250: Enable parents for pixel clocks Date: Thu, 12 Mar 2026 08:12:13 -0300 Message-ID: <20260312112321.370983-9-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent clocks are enabled during clock operations, preventing potential stability issues during display configuration. Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM= 8150 and SM8250") Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index cdfdb2cfb02b..e59cdadd5647 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -578,7 +578,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { .name =3D "disp_cc_mdss_pclk0_clk_src", .parent_data =3D disp_cc_parent_data_6, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_pixel_ops, }, }; @@ -592,7 +592,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { .name =3D "disp_cc_mdss_pclk1_clk_src", .parent_data =3D disp_cc_parent_data_6, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_pixel_ops, }, }; --=20 2.52.0