v2:
- collect tags
- bring in dispcc patch mentioned in cover letter
- add a couple new discoveries (mostly camcc related)
- add refactoring to current style (qcom_cc_driver_data)
v1: https://lore.kernel.org/all/20260309010214.224621-1-val@packett.cool/
Also bonus new question: I found
https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/489da2db487312fdaf9441056745490031b59f55
and almost included a patch adding `.skip_retention_level = true` to MMCX
in rpmhpd for the SoC, but.. it should not be necessary, right?
Just having low_svs as the requested OPP in the consumers in the DT
shooould be enough to make sure it's always at least at low_svs?
(I *thought* it might've helped with the GDSC stuck-off issue for
both Titan and MDSS but it's more likely the other fixes..)
~val
Val Packett (11):
dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs
clk: qcom: gcc-sc8180x: Add missing GDSCs
clk: qcom: gcc-sc8180x: Use retention for USB power domains
clk: qcom: gcc-sc8180x: Use retention for PCIe power domains
clk: qcom: gcc-sc8180x: Enable runtime PM support
clk: qcom: gcc-sc8180x: Refactor to use qcom_cc_driver_data
clk: qcom: dispcc-sm8250: Use shared ops on the mdss vsync clk
clk: qcom: dispcc-sm8250: Enable parents for pixel clocks
clk: qcom: camcc-sc8180x: Remove wait_val for Titan GDSC
clk: qcom: camcc-sc8180x: Add missing HW_CTRL GDSC flag
clk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data
drivers/clk/qcom/camcc-sc8180x.c | 76 ++++++-----
drivers/clk/qcom/dispcc-sm8250.c | 6 +-
drivers/clk/qcom/gcc-sc8180x.c | 126 +++++++++++++------
include/dt-bindings/clock/qcom,gcc-sc8180x.h | 5 +
4 files changed, 132 insertions(+), 81 deletions(-)
--
2.52.0