From nobody Tue Apr 7 16:36:39 2026 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37D233B6C0B; Thu, 12 Mar 2026 11:24:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314647; cv=none; b=irnF6DfjL771447QBJjf18cQcj0fl8rlINTMEIeUrIptNwyUYh55Yq4M+BASkxKo0VnaiZo31+YNcM6/9/OFAbxbNiKsa6Py7eI61I7OkXuyKi+tLe6KUTl50qG+ciMvqeHcfVVLIemHlge81ty8aAopY92yfNNbSnM7Nwb04Zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314647; c=relaxed/simple; bh=R8i5LmeS7vywoaypHJDWa8+wWER2GrTCmgrv+06xBiA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R0I0fbovNxuzv2XTl6mgR7NrTdbMPu/+6qyLGF7KGonP15Q1/lzPo63pjjCehS6tzj0xRCDBrHgc/iA/B6zEwVJSeApCpyAfRA3pzAjVwZMTWJ/CT6WmDTixzumRCHG+EjVkcVumDAsLY6bSq2jelU4MMAMVzKQbuhashaluyYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=WG8gR0f1; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="WG8gR0f1" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314642; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4l9TwGmwI62ShrR0LuMlEarvkAy091kq/V4gPz0BH3Y=; b=WG8gR0f1cLrUrA5MhTp88ICX/7OTdeXb4gEsPHK2J2ydNQZjjznQ0gWk1MJgaAs7QSJN4T HTadZS3n8XYtqTA1qeCd5ASWYhCxQ1qDqe8GZcyiNtXgWysz6gGE+tmcqFj0/tgyT1V5nn ODbjlVaAo1FkHmrPqr7+YAPeS0gvghQNfbudydSdrjHp68n7IcVXBwv714oebCrVSXneFa mCiksfb8LD7Nj8glXFr4lOMlg7KyqwRNb/TRTT7pSj6keyxJFOr3ix1G+wPhWt5SyzT+Yw K+kjlrXj3WTJk+gorWEGEM5TuK/r65tdJyowqv888aGs7F1UtnSjdd/iVS2d9A== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 01/11] dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs Date: Thu, 12 Mar 2026 08:12:06 -0300 Message-ID: <20260312112321.370983-2-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" There are 5 more GDSCs that we were ignoring and not putting to sleep, which are listed in downstream DTS. Add them. Signed-off-by: Val Packett Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-sc8180x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bind= ings/clock/qcom,gcc-sc8180x.h index b9d8438a15ff..9ed7b794aacc 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -322,5 +322,10 @@ #define USB30_MP_GDSC 8 #define USB30_PRIM_GDSC 9 #define USB30_SEC_GDSC 10 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 11 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 12 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 13 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 14 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 15 =20 #endif --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F24D43B7B87 for ; Thu, 12 Mar 2026 11:24:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314652; cv=none; b=oka7XcUDynqoMAJjZN7puIIjyk/zoeJ6gRmLa8ySVUYPm49vQ0XXmAuMuCDO5YpMNBn4woa/Ct8+DaTHjt9KX2Lwjl8keTbyIlA6INe95FnOR1Ima2me639QwdmIBvMy3oQooF00gdPU/x7ReqBBoJRIH4OZUSxO5mdY3juXVqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314652; c=relaxed/simple; bh=K93MZdYUzmd7/0/HQY2PPA45hewaXGJvSIZcGUpxKFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QEEUf6cE1n3VVG24XURCLD2NV1kGRZVuaiDmKLLyhARAuH/PBvqsnqsz5iX+k9yKPzfqr/pCm+aQzxAd843Ozgt80PyrpW4a1ZPhPpTJWdK2GQ/2PK9qHJ6B8NOHGHGfbV7Wdh6voJecmSEb3TG6PZZ/QfcGenbKXUjxw3aYU/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=db5UJaCr; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="db5UJaCr" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314648; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nzdkmw6xXbkADKQX85GvULIkWCmRl9yD5gTG9YbPFek=; b=db5UJaCrokOZ/TAis2lpUNcwYpRxumf9/giJiicjqqYv1wQyW0fmhzBpX1i0LMqCQjgAQs 6B4JFUxK3pNb8KTHoHSzPIZXuuXwQYCK0excXvKukER4xNH1G4LMrzIqe9nxAG2vUjQX+H 8SVLWqweHkLDoC0uw9z5NlDsr/p5gbbKJAxQOQ+xokTLmt+3duiiS2JQkOHUrEhCeo1FD+ l+FwH5Firbd5IAwmF11Qf+mVddJHOGdTRb8JjmsFT8SA9n0iUpaC5eU0Ab9A7/jD+8Es9G opxtZZcXHN2G0+NOkoTJ0d/RpimiBk1w4J5AIjF3VvRQnTnZfxEahZerOCE0dA== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v2 02/11] clk: qcom: gcc-sc8180x: Add missing GDSCs Date: Thu, 12 Mar 2026 08:12:07 -0300 Message-ID: <20260312112321.370983-3-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" There are 5 more GDSCs that we were ignoring and not putting to sleep, which are listed in downstream DTS. Add them. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver fo= r SC8180x") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett --- drivers/clk/qcom/gcc-sc8180x.c | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 31e788e22ab4..55dabf6259b2 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4266,6 +4266,51 @@ static struct gdsc usb30_mp_gdsc =3D { .flags =3D POLL_CFG_GDSCR, }; =20 +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc =3D { + .gdscr =3D 0x7d050, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc =3D { + .gdscr =3D 0x7d058, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc =3D { + .gdscr =3D 0x7d054, + .pd =3D { + .name =3D "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc =3D { + .gdscr =3D 0x7d05c, + .pd =3D { + .name =3D "hlos1_vote_turing_mmu_tbu0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc =3D { + .gdscr =3D 0x7d060, + .pd =3D { + .name =3D "hlos1_vote_turing_mmu_tbu1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + static struct clk_regmap *gcc_sc8180x_clocks[] =3D { [GCC_AGGRE_NOC_PCIE_TBU_CLK] =3D &gcc_aggre_noc_pcie_tbu_clk.clkr, [GCC_AGGRE_UFS_CARD_AXI_CLK] =3D &gcc_aggre_ufs_card_axi_clk.clkr, @@ -4595,6 +4640,11 @@ static struct gdsc *gcc_sc8180x_gdscs[] =3D { [USB30_MP_GDSC] =3D &usb30_mp_gdsc, [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, [USB30_SEC_GDSC] =3D &usb30_sec_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =3D &hlos1_vote_mmnoc_mmu_tbu_hf0_gds= c, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =3D &hlos1_vote_mmnoc_mmu_tbu_hf1_gds= c, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =3D &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] =3D &hlos1_vote_turing_mmu_tbu0_gdsc, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] =3D &hlos1_vote_turing_mmu_tbu1_gdsc, }; =20 static const struct regmap_config gcc_sc8180x_regmap_config =3D { --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-181.mta1.migadu.com (out-181.mta1.migadu.com [95.215.58.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE1293BC691 for ; Thu, 12 Mar 2026 11:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314659; cv=none; b=QW1VK1sSc5oFbDDLrRWW9I6pQP3Kb0ZVD+H0UW+vcyRHk4F3WSy9IPYIG2stMfehGAwCMCzgLeYvw33Sj4wttCf28btiqWlEmgf5UfO0N7Zo037QjE6GCdocds9AV5TPNOehgkaxQB/egRnnaXh7Ig6wMy31mSKjU0PUB97IsBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314659; c=relaxed/simple; bh=fMF1zjZtYW/LRVY5l3KylMX1H6YZCmOAWejgja5oIko=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N+EgKIR7FJ8CoMkbLEHOauyfgpHm61Nd68o41GFZnB+0I7zAu7IADxZZTGoy1MYN6Gx2YS36DZobaE7TGGyWkq5p5XgWdn+KTTcZ+54iIIxPInDLFnEE8Pe2gVFpihso/uvx6osp9O0gbps5GTio3BmI5Vn/gEDAYcYE0HoKcr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=Ysb6Dw4N; arc=none smtp.client-ip=95.215.58.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="Ysb6Dw4N" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314653; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Cj30hm5HNRXjPMriu/QBk8vWAAIdNsORZxQhVcrPE7k=; b=Ysb6Dw4N1UeM3VN2A8qozSkkIOfpxv3AmBDoJX1u78yU95FQIvQBXz64LSWs+of1uVTZZo SGtZpd8EYeipWTY8pGjeit7WtZ9QUOAhDVWouzZEA3yRH3XhgpeTM6mpkug/TMA0mMU3qa hNV31q3MLrZPvsyt5t/AXWL+dOLfzHIaMUhg6y5RqqJ4LCi6gz0V8fyhBGjsEga6fJwyON WTfYAFgMzRbqFgXWp3RLXV6wj+sxhP5gvnWTEotWrlTHuc4D0FbrdgG9mJhYY1NWtrSUGN ZmjiUq0jUWu4wTluj76YH7qpRYRLtDgqZ3IX23QQF0zz8RJT49r5kWuzX26F/w== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v2 03/11] clk: qcom: gcc-sc8180x: Use retention for USB power domains Date: Thu, 12 Mar 2026 08:12:08 -0300 Message-ID: <20260312112321.370983-4-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The USB subsystem does not expect to lose its state on suspend: xhci-hcd xhci-hcd.0.auto: xHC error in resume, USBSTS 0x401, Reinit usb usb1: root hub lost power or was reset (The reinitialization usually succeeds, but it does slow down resume.) To maintain state during suspend, the relevant GDSCs need to stay in retention mode, like they do on other similar SoCs. Change the mode to PWRSTS_RET_ON to fix. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver fo= r SC8180x") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett --- drivers/clk/qcom/gcc-sc8180x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 55dabf6259b2..b116a9c0b2d9 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4172,7 +4172,7 @@ static struct gdsc usb30_sec_gdsc =3D { .pd =3D { .name =3D "usb30_sec_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 @@ -4190,7 +4190,7 @@ static struct gdsc usb30_prim_gdsc =3D { .pd =3D { .name =3D "usb30_prim_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 @@ -4262,7 +4262,7 @@ static struct gdsc usb30_mp_gdsc =3D { .pd =3D { .name =3D "usb30_mp_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAD373B7B87 for ; Thu, 12 Mar 2026 11:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314661; cv=none; b=uscQiprPjUfEaiuOruiEr5W7ur9FNJEIO0rfB2l/isBbNwkHPtBSFJo3N9Y4WAI8zD/2BeghXgXHgLlPeA4bTCTK6iUwQk7PmdXBtWwC+AiRPfFVtF1kEPqHr1MTn/U/5vuIwfXzh3SAT1WZQgroCTlfmBT5l2Rp2Q3Id2lZaCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314661; c=relaxed/simple; bh=/j/Ambs/rTjtGg1d+Jw/qA/S3EU/8rQakW2oo8t7n1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SWV2SVlx4pxnAqsYBqpIvlgwx07sIDdJNSPwSzRfZcvZgvEHyhRZieJffawyZfITHkEQgeiR46BZ4BJdVeuVyMx8Mw+EDbmne6T2m4hCPdmJVSIsXU8QtN5ioPTELPSRxqOAZ+lPXvY3N5m8N13taiQnz3Jo9ENgGn5iI5Yb1zg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=vLR1kVut; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="vLR1kVut" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314657; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uYmcpjf96fKpETw1f+1vsmEXvLg+reOV8ikWblNG5mY=; b=vLR1kVutshNofmpimaaqEvaxrbHQuwQXlcWQXHE+CUZpa2N/IfjNTSOViKHJU7SNz9FktJ YMDjabUFc+CNd60BgdRMa7R5yiBriqdMPj0mbkxhcB9IxfdnRlVqksCdwEAyfxwe/C0ljL g3b8CgyPQ8lxPvtWd4GU5aQ4abpl/nP/8N4XXg6M7nQlaw8/7onyM4vPa+HwPtL500REU9 XkwfU6YhjNc41N/YNq9MxSaT2lH12Rv/ppiVuWLTH7ns7KnbQrn/djpYo6zWVmuAMRBkgx AYt2at4NuuCkATJ23vf4dDoqOdHV+LejAVNrMemhnnH8INSlCaM8qwPxe+EZUA== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Subject: [PATCH v2 04/11] clk: qcom: gcc-sc8180x: Use retention for PCIe power domains Date: Thu, 12 Mar 2026 08:12:09 -0300 Message-ID: <20260312112321.370983-5-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" As the PCIe host controller driver does not yet support dealing with the loss of state during suspend, use retention for relevant GDSCs. This fixes the link not surviving upon resume: nvme 0002:01:00.0: Unable to change power state from D3cold to D0, devi= ce inaccessible nvme nvme0: controller is down; will reset: CSTS=3D0xffffffff, PCI_STAT= US read failed (134) nvme 0002:01:00.0: Unable to change power state from D3cold to D0, devi= ce inaccessible nvme nvme0: Disabling device after reset failure: -19 Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver fo= r SC8180x") Reviewed-by: Dmitry Baryshkov Signed-off-by: Val Packett Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam --- drivers/clk/qcom/gcc-sc8180x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index b116a9c0b2d9..4095a1f54a09 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4199,7 +4199,7 @@ static struct gdsc pcie_0_gdsc =3D { .pd =3D { .name =3D "pcie_0_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 @@ -4226,7 +4226,7 @@ static struct gdsc pcie_1_gdsc =3D { .pd =3D { .name =3D "pcie_1_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 @@ -4235,7 +4235,7 @@ static struct gdsc pcie_2_gdsc =3D { .pd =3D { .name =3D "pcie_2_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 @@ -4253,7 +4253,7 @@ static struct gdsc pcie_3_gdsc =3D { .pd =3D { .name =3D "pcie_3_gdsc", }, - .pwrsts =3D PWRSTS_OFF_ON, + .pwrsts =3D PWRSTS_RET_ON, .flags =3D POLL_CFG_GDSCR, }; =20 --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9808F3BC688 for ; Thu, 12 Mar 2026 11:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314665; cv=none; b=GBDnWcv25FJ7WIaFS7xYocKOJVGJfK/bQz6GL6C9mQoxFA7MdVtq22EzuWip5gM0+0d96gQn/0FloyidJjA+U0DGHIt9EGJ33ek779jTatBIDq21tcQ7bXLwnShZB/VzNfu4wlukTs4hZpFsu6kZ6L6kvj6lC5BRsmopbuxc4Pw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314665; c=relaxed/simple; bh=cgaPZinUPDr1PYA2GyKMdYtFxWLsPXtHju41DxXVaTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BjDdi4HgE8lPHBwTFpdEbrsh5E9B7CF8G4gOGZCyQDpLsij9ME6Zvs62bUyIF/pEbQIrJp+9z7lHsjBjkLTC2MRyYJg2UKjR386Zjz56YG4OG9hSJcEltO88qOxtGcf0m5KyI0T10meIXjPrIC6ylt+gPNJ5pNNBx23XIjX/xUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=Okx812Rt; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="Okx812Rt" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CeQ/ayI+gqt2blZgg3ZnKYaoMVG/Kc0EQV8JnYiTbYA=; b=Okx812RtnWpBrMaKI+Tws5cKkhgFP3UCX+i01EtVRQAPM/7IfDbXc4rBMEf40+UPg3sOZc 4VhDnAjngZhmsT8PhtebTL/WcecLAwv3K9T+2HzdYdIDc8lOepDbp1NgWxQe3F4kqy9VJb E4D2GnVAV+/z+Ai0Aj13ru4pbU3TEFstc3WKhG/SnRiGNZumRT48D6l4tmUmiMAmBa7JuG mt376acdulvW9dvaI7qzE5PA2lDLvKlEq6mu67eHLKQualX1eBvuBe9zRfWt1ltKDxT7tV rjKsz+pT+uDE4bgU8dNs8gbcaB0yPZoY8MvOpbIJIB332vaIAwzbS2lTKpn9Zw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/11] clk: qcom: gcc-sc8180x: Enable runtime PM support Date: Thu, 12 Mar 2026 08:12:10 -0300 Message-ID: <20260312112321.370983-6-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The GCC block on SC8180X is powered by the CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sc8180x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 4095a1f54a09..2888c4ebd5e8 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4663,6 +4663,7 @@ static const struct qcom_cc_desc gcc_sc8180x_desc =3D= { .num_resets =3D ARRAY_SIZE(gcc_sc8180x_resets), .gdscs =3D gcc_sc8180x_gdscs, .num_gdscs =3D ARRAY_SIZE(gcc_sc8180x_gdscs), + .use_rpm =3D true, }; =20 static const struct of_device_id gcc_sc8180x_match_table[] =3D { --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 167513BD25F for ; Thu, 12 Mar 2026 11:24:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314669; cv=none; b=V+FGahtdemPIGWTSfEiJ33iAGgFmg6U91MbiQnJd+aWB6WNWItYjWSzZIBsonBmiLM9o3a+DTD1tlOv5tyygIrWpeRr/upeyYUH/cChjFlyZb9Swd5SmhWIsYb8hNQp2txTu2OpyBdiM+Pdkvm+UQxscGgEF16Nrv4eQAbVBlbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314669; c=relaxed/simple; bh=YBOjOezRXgSWTxZGDoyuvFIEMJrV2161nYB8kYXjU8w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PINqLYOaiIRBSv1cpoT3jld1nvIoZs5Rn1ujBKA+oz2YiI8oDRxGXNSzCh+YdPE4+5fc99phN+emtkdeZvofKrcpSP1EnIGcXOt9Ptpn9jW5J92e+9gz9HrCdaJ1yWvAHw91BfGbJ/16xyDGoSY7o3RPVIf2v3UMgefYFT5dZMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=ZNpMw/ie; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="ZNpMw/ie" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ffXIwn/SipTvQjaI8IylarOlKCDGzLC/zRz4bzxuSs=; b=ZNpMw/ieXOT5ObySb1m1BNRS57ZVqFAoyoF2sppfKUNESCbPJ83auE8qBEXwYgfrDsCliD A/WWsxntqfXRmgJD8NGpES2OokU+sL2Yct5fFTpc3VyulCT8GoCrZecYMBcmjlDXU1wYmV D8ElThhu/7R2iazVY0pcfawU6pMMVNKO8bOJ7JW0gcehUvnP9dAiAZPAZubyEQAa0UQ0b1 cHPrvTAkKZhko4t+sbO993EJLXF2KQWT8z1NCA6q/ZkVfsFdb+ZnXhtx6BOXu0VQ8K8a3m 3ywMvfHq3s8HkRuvGyYlXL3B2V4vFl3BAVX+o22IgvslUC4wZinL44f4nejCQw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/11] clk: qcom: gcc-sc8180x: Refactor to use qcom_cc_driver_data Date: Thu, 12 Mar 2026 08:12:11 -0300 Message-ID: <20260312112321.370983-7-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Use a qcom_cc_driver_data struct instead of a long custom probe callback to align with modern qcom/gcc-*.c style. No functional change intended. Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sc8180x.c | 61 +++++++++++++++++----------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 2888c4ebd5e8..88b95d5326d9 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4605,7 +4605,7 @@ static const struct qcom_reset_map gcc_sc8180x_resets= [] =3D { [GCC_VIDEO_AXI1_CLK_BCR] =3D { .reg =3D 0xb028, .bit =3D 2, .udelay =3D 1= 50 }, }; =20 -static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { +static const struct clk_rcg_dfs_data gcc_sc8180x_dfs_clocks[] =3D { DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), @@ -4647,6 +4647,19 @@ static struct gdsc *gcc_sc8180x_gdscs[] =3D { [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] =3D &hlos1_vote_turing_mmu_tbu1_gdsc, }; =20 +static u32 gcc_sc8180x_critical_cbcrs[] =3D { + 0xb004, /* GCC_VIDEO_AHB_CLK */ + 0xb008, /* GCC_CAMERA_AHB_CLK */ + 0xb00c, /* GCC_DISP_AHB_CLK */ + 0xb040, /* GCC_VIDEO_XO_CLK */ + 0xb044, /* GCC_CAMERA_XO_CLK */ + 0xb048, /* GCC_DISP_XO_CLK */ + 0x48004, /* GCC_CPUSS_GNOC_CLK */ + 0x48190, /* GCC_CPUSS_DVM_BUS_CLK */ + 0x4d004, /* GCC_NPU_CFG_AHB_CLK */ + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ +}; + static const struct regmap_config gcc_sc8180x_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -4655,6 +4668,21 @@ static const struct regmap_config gcc_sc8180x_regmap= _config =3D { .fast_io =3D true, }; =20 +static void clk_sc8180x_regs_configure(struct device *dev, struct regmap *= regmap) +{ + /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); +} + +static struct qcom_cc_driver_data gcc_sc8180x_driver_data =3D { + .clk_cbcrs =3D gcc_sc8180x_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_sc8180x_critical_cbcrs), + .dfs_rcgs =3D gcc_sc8180x_dfs_clocks, + .num_dfs_rcgs =3D ARRAY_SIZE(gcc_sc8180x_dfs_clocks), + .clk_regs_configure =3D clk_sc8180x_regs_configure, +}; + static const struct qcom_cc_desc gcc_sc8180x_desc =3D { .config =3D &gcc_sc8180x_regmap_config, .clks =3D gcc_sc8180x_clocks, @@ -4664,6 +4692,7 @@ static const struct qcom_cc_desc gcc_sc8180x_desc =3D= { .gdscs =3D gcc_sc8180x_gdscs, .num_gdscs =3D ARRAY_SIZE(gcc_sc8180x_gdscs), .use_rpm =3D true, + .driver_data =3D &gcc_sc8180x_driver_data, }; =20 static const struct of_device_id gcc_sc8180x_match_table[] =3D { @@ -4674,35 +4703,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table); =20 static int gcc_sc8180x_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - regmap =3D qcom_cc_map(pdev, &gcc_sc8180x_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Keep some clocks always-on */ - qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ - qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ - qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ - - /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ - regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, - ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) - return ret; - - return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap); + return qcom_cc_probe(pdev, &gcc_sc8180x_desc); } =20 static struct platform_driver gcc_sc8180x_driver =3D { --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76FBC3BE64B for ; Thu, 12 Mar 2026 11:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314673; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CzW6GgYT0Hq52fgkX18bHoLKVtz4DvDWuePNOqfPfZY=; b=epMDnH1MBr9n2q5qyz6OUtR5PLmPfJKXqHht82KSgIV9rMPdn68oqjkSukJIenyrCp5mTL hx3IjIvHHG6WZ5GqIlGavqdkPjW5RH/SfyyCdwk5lix6RWibJIZOYFcCXnz8/xLBFRtXtq +sbl4A2EPZpdEIwJWAtq+x01fBPkAvgtN+zgLR1k0J3aNTn7RBEEtwABtVCmHcdo5RZ3nx lPoBIXdAf/xWvolCabVsfRjwnwDYoExjovcjXbs21ehO+3CIaVt+nHnVsXd4EjfweZoi3k mxuzQoZ1VhSZMZm4w1UdKldKGMVAwoR/Yi+Fa8VeDG2sCiK4Cg8cprkyTyhNKQ== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/11] clk: qcom: dispcc-sm8250: Use shared ops on the mdss vsync clk Date: Thu, 12 Mar 2026 08:12:12 -0300 Message-ID: <20260312112321.370983-8-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" mdss_gdsc can get stuck on boot due to RCGs being left on from last boot. As a fix, commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") introduced a callback to ensure the RCG is off upon init. However, the fix depends on all shared RCGs being marked as such in code. For SM8150/SC8180X/SM8250 the MDSS vsync clock was using regular ops, unlike the same clock in the SC7180 code. This was causing display to frequently fail to initialize after rebooting on the Surface Pro X. Fix by using shared ops for this clock. Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM= 8150 and SM8250") Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index 8f433e1e7028..cdfdb2cfb02b 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -632,7 +632,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src =3D { .parent_data =3D disp_cc_parent_data_1, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_1), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54FEE3BF674 for ; Thu, 12 Mar 2026 11:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314678; cv=none; b=oy+iUcPgGyO0UMdW7BXwcg47x0m4FIsIBEtAtFMBN+fVQ+0yJGKZvUim7v0tsVxPOUs5J0Qrg9jpBaJ2kv8MWey0H8Zxry99jR352fNf/ydVN22SIJsTWK74uSNOSnO32ijIHSUuzoPA1Edw2YmlC7cJmEJzduhi52p+4Lmx/mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314678; c=relaxed/simple; bh=uYs3JHAd/jxTQEVzpORrcnhgntV0JK5nGBynUCea0wM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GkvibpBXF4ebPzENdYqZCNmV9rNF2g+qh1ObACp1iDSpjwmV8e8qp1lH1N/pjGqK68ZcOWcrn/LwBWBfWJOiecyU3ETCWuCa+zMhK5fuyRW/JJUCWsGCV1URBuVsXrNtbh1MkuvRy7/VF/J7aQhYxdUlIu/EaCf6HzV07BF7IEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=QOqc7FP7; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="QOqc7FP7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c6bg3vbkQkQwI35FQJs6xm3Hr9kxqB+NBTc/GQ3vahI=; b=QOqc7FP7egtUy4YxR8zfb3602SOEEB9rhWA/QnV+2f5JaKXfW1kyJE8VTartiIybviRMdL eIfihcVwp2HsuMfqgetT4XofMWV0mr8sHWPW+su/TkpNUKwZbgkraCBN32xpkSfOYpTPQe e+dPBsGYka3cZ5r1M3jXy+YD9JluGTvMUqg4kItug+w4kH2rwal9luVaeGejllx/0Z+EMH 8rsnyP3xZ+e+26zbDtJ7/n+GWTS2LN3trI1BC2KWTPT5PJN2HG1nyI9JQoYkPh9CH7nhL9 Q3PDS2HCIA6LH3e6fUvh0SELS6WFLem1VFYehe/lVds7PUFqhw1JAzMErDZi8w== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Jonathan Marek Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/11] clk: qcom: dispcc-sm8250: Enable parents for pixel clocks Date: Thu, 12 Mar 2026 08:12:13 -0300 Message-ID: <20260312112321.370983-9-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent clocks are enabled during clock operations, preventing potential stability issues during display configuration. Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM= 8150 and SM8250") Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index cdfdb2cfb02b..e59cdadd5647 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -578,7 +578,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src =3D { .name =3D "disp_cc_mdss_pclk0_clk_src", .parent_data =3D disp_cc_parent_data_6, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_pixel_ops, }, }; @@ -592,7 +592,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src =3D { .name =3D "disp_cc_mdss_pclk1_clk_src", .parent_data =3D disp_cc_parent_data_6, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_6), - .flags =3D CLK_SET_RATE_PARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops =3D &clk_pixel_ops, }, }; --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86BF43BBA0E for ; Thu, 12 Mar 2026 11:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314684; cv=none; b=iWy9LtBFqZg+VDSxxjLWgJP43bHfrwrE611UVDYi0kqE2S7TEAIBYek43ycRJfTjcX0Rr3kWzpV3pY2OZztsbJyNDvjMM1AcYhAK992Jv+oYDpPibzABsW0YNgSXyt8A0wELvvxVXgmyLY8MjkmWcTEADzGSf318bae/RyRe4+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314684; c=relaxed/simple; bh=h5l7xTESRGG/9LA6K44BUKx7xT5XlvcESjqI4YstRtQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XQIfkJUc60tAQet3+wn2p+c27SQGFNk7kpNwNcq/s34zJXQ5waQVucBOrw/ehfFtaY8KPGqOGgcKDN6/gRNGUGYTuD53x0a4Gd8KGU7uMFU3x3MVXxo3YBz4N9ZMRv5GMcr6gyX3reyq1zbRAkL9pKbiK3SSgiWeqhZZE6Y7WBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=QNxjmAaW; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="QNxjmAaW" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OEYw1hMn+rPN4lG8dtzxXDk53oCQisDbgFmhbdO9lCM=; b=QNxjmAaWGLM/ajhmOBbHnVGrHTO4RpU46uCQwUSyHAU2YTTcUkozDtHhJSvtuKqmI+rwmQ I5S4XPa5KXqw8q1Y0/wbdsSeGaO6p8MaEYWBchEjR93WsSQBLimJEs6o70iQA6ZhA3Gs2J 77u6ePlYLGY7kOWBFfokkSR1IIaw37ucAVkwcBSq4Cymswy6rBB5sgHDLTEXv5aA78w9+S 9VJRWfOzA10NKMjUqFvhav3WC8bq6nHGowq/1c5ddPfiUxjPln7I01qjq9L27y7y629oVe 428ODD02imj9SLVkz0nbsO80HLQShi1hJSjPPQ7saVrn1bOApKwlMxA2ElJnKw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Satya Priya Kakitapalli , Dmitry Baryshkov Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/11] clk: qcom: camcc-sc8180x: Remove wait_val for Titan GDSC Date: Thu, 12 Mar 2026 08:12:14 -0300 Message-ID: <20260312112321.370983-10-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" These values seem to have been copied from newer SoCs, but e.g. SC7180 and SDM845 do not use them. They seem to play a role in causing the "titan_top_gdsc stuck at off" errors on boot on the Surface Pro X. Remove to fix. Fixes: 691f3413baa4 ("clk: qcom: camcc-sc8180x: Add SC8180X camera clock co= ntroller driver") Signed-off-by: Val Packett --- drivers/clk/qcom/camcc-sc8180x.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8180x.c b/drivers/clk/qcom/camcc-sc81= 80x.c index 388fedf1dc81..cd4c40a81c28 100644 --- a/drivers/clk/qcom/camcc-sc8180x.c +++ b/drivers/clk/qcom/camcc-sc8180x.c @@ -2538,9 +2538,6 @@ static struct clk_branch cam_cc_mclk7_clk =3D { =20 static struct gdsc titan_top_gdsc =3D { .gdscr =3D 0xc1bc, - .en_rest_wait_val =3D 0x2, - .en_few_wait_val =3D 0x2, - .clk_dis_wait_val =3D 0xf, .pd =3D { .name =3D "titan_top_gdsc", }, --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-174.mta1.migadu.com (out-174.mta1.migadu.com [95.215.58.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 116243BD64B for ; Thu, 12 Mar 2026 11:24:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314689; cv=none; b=NVpn4mKiDeD3HIXqYuXaBBLGuymftTlfW21uDd5P/lHCqeJLjSLLiNnk9Qh0asv5P0T+zf8gK1V3C3qMAgm7CWnjzfoKdsEJXdUTh5ZJOMiRwNkrWaHPC/mSDw0gZrgYQQKchRjbFNlMnjKxGOGHO9BeKoENCv7TYKIgpN1qO1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314689; c=relaxed/simple; bh=vi3l57rFdQN9o6dYFz4oHBnQnb11V1l9VfNmYa5ReRU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X2DZ7mYfAG/saVNNV0h9Kla04im1g7CEiBHUcw5ECND8FG4DT7taukalS9r93syQonVHeg6ISqwPmNTyLEZE+DaZhuinHj8Cgm4SfpRN141A/r/JUvXTXo3ZiV+jrveQzCvOqv+a2wGD2zm9W64lwfPgRPtZssBuELcKkJDQedU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=DBqgUKhJ; arc=none smtp.client-ip=95.215.58.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="DBqgUKhJ" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qRgEFaLoplAf78NDUsUX00O6rpYN8XYlndl7+r59PiQ=; b=DBqgUKhJ52pMAze8FlM7/cDnMrTp+FpePn+nCkzju7pyr+mXRai7VumOaDtWeqk4Ly5uo9 satgmvbcAvFhlapkQwEIQG8Y3323STpFXTPJItlRdF06crDpE1jYe658OExlH4Q5+3P0r0 2SbaiXajgBYPzCPiIMS6zZP2DPgMhwpWW6OTaia99eyRBZWl/jqtJoCxz+nzgcCu5Ct6YH 0cB2eY0yMzVio9iCrn2EY7a93KxzTHOhVrOg7LSVE3XxeMzknHCOEzI47ALsG+xv4Z1c8j wcI6511iDviAU2MOP8IEjoO3OCAvHWlgolshOnG/bXkOCPSjY5uNyGH/85OBqw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Vladimir Zapolskiy , Dmitry Baryshkov , Satya Priya Kakitapalli Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/11] clk: qcom: camcc-sc8180x: Add missing HW_CTRL GDSC flag Date: Thu, 12 Mar 2026 08:12:15 -0300 Message-ID: <20260312112321.370983-11-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" In all other Qualcomm SoC camcc drivers, the BPS and IPE GDSCs use the HW_CTRL flag, but it was missing on SC8180X. Fix by setting it on all applicable GDSC entries. Fixes: 691f3413baa4 ("clk: qcom: camcc-sc8180x: Add SC8180X camera clock co= ntroller driver") Signed-off-by: Val Packett --- drivers/clk/qcom/camcc-sc8180x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8180x.c b/drivers/clk/qcom/camcc-sc81= 80x.c index cd4c40a81c28..67b2055bd212 100644 --- a/drivers/clk/qcom/camcc-sc8180x.c +++ b/drivers/clk/qcom/camcc-sc8180x.c @@ -2555,7 +2555,7 @@ static struct gdsc bps_gdsc =3D { }, .pwrsts =3D PWRSTS_OFF_ON, .parent =3D &titan_top_gdsc.pd, - .flags =3D POLL_CFG_GDSCR, + .flags =3D HW_CTRL | POLL_CFG_GDSCR, }; =20 static struct gdsc ife_0_gdsc =3D { @@ -2620,7 +2620,7 @@ static struct gdsc ipe_0_gdsc =3D { }, .pwrsts =3D PWRSTS_OFF_ON, .parent =3D &titan_top_gdsc.pd, - .flags =3D POLL_CFG_GDSCR, + .flags =3D HW_CTRL | POLL_CFG_GDSCR, }; =20 static struct gdsc ipe_1_gdsc =3D { @@ -2633,7 +2633,7 @@ static struct gdsc ipe_1_gdsc =3D { }, .pwrsts =3D PWRSTS_OFF_ON, .parent =3D &titan_top_gdsc.pd, - .flags =3D POLL_CFG_GDSCR, + .flags =3D HW_CTRL | POLL_CFG_GDSCR, }; =20 static struct clk_regmap *cam_cc_sc8180x_clocks[] =3D { --=20 2.52.0 From nobody Tue Apr 7 16:36:39 2026 Received: from out-171.mta1.migadu.com (out-171.mta1.migadu.com [95.215.58.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C1FC3BED54 for ; Thu, 12 Mar 2026 11:24:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314695; cv=none; b=VrHsA+BQ+7Yo9ZZYzVq2aY5FecvLf+Ko7Idy9ZbmMxP60PQ161N09LpKR1XFkfH+d+26D/SDSMsghzuvM8ZqHJ86cDLnoJskWEAk/d4SK2PRm4b48kTRYTt/Jn4kwun1LP5xomwUgRpGVWliGCGP8MEeGm2jmIRYDUZ2WP47KeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773314695; c=relaxed/simple; bh=SHsUWsOET7NnIcPa0jYYlqLqNbSur5ziIMfCgbWbCrM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fVIW+FHxPl/S968avx+iFbwap2f6lEJV89W9Gtv8DZPNv46uEs91N3440GvpqsWoKoDR8GZp1NvxxxSY/KJWnu3hFpi5gJXauYGt2fGTRSnvaiGYATDuPTY1bJ4kTrPysNL3Q9SOXT5zHHvEBOPShjcilvYfGst0NdZHgPQnZ7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=oILVuSdh; arc=none smtp.client-ip=95.215.58.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="oILVuSdh" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1773314692; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oLUzWeEcNPzK2JN8Mrg4INR+pFs0gxDSLlWR+/wJ15k=; b=oILVuSdhrgvJcsjqzi4KE/t0d6Jm7LKOudVqwAu8zyIf3a2VLHUpesausSf7eyYyA324SV F3uGERqDjBOYunaYWk3fOOSg0XGqoRFCDPGgMpZzEGjRu2c3c8D/ju6Ubw6OIcpHEZi0S2 haNsyPJGyOsEIHUlTJhcK5fMnvmPlFn8mcS3jdIn5NJWZoHWyEswALXBtteeExg/LIHXuC AbzzOfRyUug48xTtfJL3iK40b5DrtYfNftvLtZj9RjsRhjqsqCcvtnWS0i+/eUTazPwwA5 jNdkPOIM4Y3JiP0gOSpBXmoRvN5zPy6PzDhw0/qWzCN+ud5EmIKdgeMb7Npjuw== From: Val Packett To: Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: Val Packett , Konrad Dybcio , Johan Hovold , Manivannan Sadhasivam , Dmitry Baryshkov , Maximilian Luz , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/11] clk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data Date: Thu, 12 Mar 2026 08:12:16 -0300 Message-ID: <20260312112321.370983-12-val@packett.cool> In-Reply-To: <20260312112321.370983-1-val@packett.cool> References: <20260312112321.370983-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Use a qcom_cc_driver_data struct instead of a long custom probe callback to align with modern qcom/gcc-*.c style. No functional change intended. Signed-off-by: Val Packett Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/camcc-sc8180x.c | 67 +++++++++++++++----------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8180x.c b/drivers/clk/qcom/camcc-sc81= 80x.c index 67b2055bd212..bbd7add69cb0 100644 --- a/drivers/clk/qcom/camcc-sc8180x.c +++ b/drivers/clk/qcom/camcc-sc8180x.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -63,6 +62,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -138,6 +138,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -167,6 +168,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D regera_vco, .num_vco =3D ARRAY_SIZE(regera_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA], @@ -219,6 +221,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -248,6 +251,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -277,6 +281,7 @@ static const struct alpha_pll_config cam_cc_pll5_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x4078, + .config =3D &cam_cc_pll5_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -306,6 +311,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x40f0, + .config =3D &cam_cc_pll6_config, .vco_table =3D trion_vco, .num_vco =3D ARRAY_SIZE(trion_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], @@ -2810,6 +2816,21 @@ static const struct qcom_reset_map cam_cc_sc8180x_re= sets[] =3D { [CAM_CC_MCLK7_BCR] =3D { 0x50e0 }, }; =20 +static struct clk_alpha_pll *cam_cc_sc8180x_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, +}; + +static u32 cam_cc_sc8180x_critical_cbcrs[] =3D { + 0xc1e4, /* CAM_CC_GDSC_CLK */ + 0xc200, /* CAM_CC_SLEEP_CLK */ +}; + static const struct regmap_config cam_cc_sc8180x_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2818,6 +2839,13 @@ static const struct regmap_config cam_cc_sc8180x_reg= map_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_sc8180x_driver_data =3D { + .alpha_plls =3D cam_cc_sc8180x_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sc8180x_plls), + .clk_cbcrs =3D cam_cc_sc8180x_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sc8180x_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sc8180x_desc =3D { .config =3D &cam_cc_sc8180x_regmap_config, .clks =3D cam_cc_sc8180x_clocks, @@ -2826,6 +2854,8 @@ static const struct qcom_cc_desc cam_cc_sc8180x_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sc8180x_resets), .gdscs =3D cam_cc_sc8180x_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sc8180x_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sc8180x_driver_data, }; =20 static const struct of_device_id cam_cc_sc8180x_match_table[] =3D { @@ -2836,40 +2866,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sc8180x_match_table); =20 static int cam_cc_sc8180x_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sc8180x_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_trion_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_trion_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0xc200); /* CAM_CC_SLEEP_CLK */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sc8180x_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; + return qcom_cc_probe(pdev, &cam_cc_sc8180x_desc); } =20 static struct platform_driver cam_cc_sc8180x_driver =3D { --=20 2.52.0