The rsten register is part of the system controller address range.

This register controls the reset sources allowed to reset the system.
Among them, watchdogs can be configured to be able to perform this
reset.

Introduce a new helper r9a06g032_sysctrl_enable_rst() in order to set
specific sources in the rsten register from the watchdog driver.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 drivers/clk/renesas/r9a06g032-clocks.c        | 32 +++++++++++++++++++
 include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 +++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 7407a4183a6c..517d46ff150e 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -705,6 +705,38 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
 }
 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
 
+int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
+{
+	unsigned long flags;
+	u32 rsten;
+	u32 val;
+
+	switch (rst_src) {
+	case R9A06G032_RST_WATCHDOG_CA7_0:
+		val = R9A06G032_SYSCTRL_WDA7RST_0;
+		break;
+
+	case R9A06G032_RST_WATCHDOG_CA7_1:
+		val = R9A06G032_SYSCTRL_WDA7RST_1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (!sysctrl_priv)
+		return -EPROBE_DEFER;
+
+	spin_lock_irqsave(&sysctrl_priv->lock, flags);
+
+	rsten = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN);
+	writel(rsten | val, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN);
+
+	spin_unlock_irqrestore(&sysctrl_priv->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_enable_rst);
+
 static void clk_rdesc_set(struct r9a06g032_priv *clocks,
 			  struct regbit rb, unsigned int on)
 {
diff --git a/include/linux/soc/renesas/r9a06g032-sysctrl.h b/include/linux/soc/renesas/r9a06g032-sysctrl.h
index 066dfb15cbdd..25542b49eb55 100644
--- a/include/linux/soc/renesas/r9a06g032-sysctrl.h
+++ b/include/linux/soc/renesas/r9a06g032-sysctrl.h
@@ -4,8 +4,20 @@
 
 #ifdef CONFIG_CLK_R9A06G032
 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val);
+
+enum r9a06g032_sysctrl_rst_src {
+	R9A06G032_RST_WATCHDOG_CA7_0,
+	R9A06G032_RST_WATCHDOG_CA7_1,
+};
+
+int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src);
+
 #else
 static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; }
+static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__ */
-- 
2.53.0