From nobody Wed Apr 8 06:05:16 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70AE13D47BC for ; Tue, 10 Mar 2026 17:33:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164001; cv=none; b=nKI4sch/USMVkbfawKEjAb3CWRpyJS7jCiBENuF+moMpqyrvh3cqQcst9oAOkosYpZnplxWrRucJirqdX41sc3LXtIsSzl22m/Gff8E1l/gDQ+4PZspKh43+afQfyB7VcHVRJP4wSRAlQAbW48lr4Dl9HSDqz42x3RrOiwOr9nM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164001; c=relaxed/simple; bh=uTxcEX9dtGW13fmgVaUG0TJvPmOSE3Up0iusG94HGDg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bQY7IBq8wbK5vC0aeqMujssQqOJZCBhqrIrtZ5OvKLNPYiWF1Zz0+ZDXZutqN71Dvjzi7tUj4RnayuG2SqAapLXW+tDv3gVt3hmwYoEhV92YGxlb0igZDDy0nqT+6Th8BGvnoOY0u7c3GfwWr6wAA42aAGdJV753zo9zxG5zdPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=kVKvo+Zm; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kVKvo+Zm" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 0DC34C4043F; Tue, 10 Mar 2026 17:33:40 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2848D60002; Tue, 10 Mar 2026 17:33:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EE2C61036987B; Tue, 10 Mar 2026 18:33:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773163997; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=QMk4xKL7rwkuDzgFTLggs6bTGets20VvaMmysYufXCE=; b=kVKvo+ZmV7YIFp+k4mo4GdYzH11QVgENz5yaPJhCW6d1hvMyvr7pvybDtMT2eGfWY2+aQu YJbwZs1Ro/7nShbvmvqB0h69b07vzVHxNgQtusxPxLNDYytA1PJbH06GcLkqbgzStTfIYe vPOPXjc9S70LSYK/dTB/OmX9lgesrcXOmePFF2Iu2gRehDgNuIzB15qqoBClvolIZkMLF3 FyNDSzWPyYm07cQp4pNJOzMfUeKV/fEq7vj1JS8Cdvo4nOagL7HGA9uwDM+lS4HPk+2zbG kQYdOOL9hs9+j4nHWsrOFqFOsNpZYU3AHCWSwJ3fs9vo6oB5Wq+UentaTjN+xA== From: "Herve Codina (Schneider Electric)" To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm , Wolfram Sang Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni , "Herve Codina (Schneider Electric)" Subject: [PATCH 4/5] clk: renesas: r9a06g032: Introduce a helper to set rsten register Date: Tue, 10 Mar 2026 18:32:45 +0100 Message-ID: <20260310173249.161354-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260310173249.161354-1-herve.codina@bootlin.com> References: <20260310173249.161354-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The rsten register is part of the system controller address range. This register controls the reset sources allowed to reset the system. Among them, watchdogs can be configured to be able to perform this reset. Introduce a new helper r9a06g032_sysctrl_enable_rst() in order to set specific sources in the rsten register from the watchdog driver. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/clk/renesas/r9a06g032-clocks.c | 32 +++++++++++++++++++ include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 +++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r= 9a06g032-clocks.c index 7407a4183a6c..517d46ff150e 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -705,6 +705,38 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) } EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); =20 +int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src) +{ + unsigned long flags; + u32 rsten; + u32 val; + + switch (rst_src) { + case R9A06G032_RST_WATCHDOG_CA7_0: + val =3D R9A06G032_SYSCTRL_WDA7RST_0; + break; + + case R9A06G032_RST_WATCHDOG_CA7_1: + val =3D R9A06G032_SYSCTRL_WDA7RST_1; + break; + default: + return -EINVAL; + } + + if (!sysctrl_priv) + return -EPROBE_DEFER; + + spin_lock_irqsave(&sysctrl_priv->lock, flags); + + rsten =3D readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN); + writel(rsten | val, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN); + + spin_unlock_irqrestore(&sysctrl_priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_enable_rst); + static void clk_rdesc_set(struct r9a06g032_priv *clocks, struct regbit rb, unsigned int on) { diff --git a/include/linux/soc/renesas/r9a06g032-sysctrl.h b/include/linux/= soc/renesas/r9a06g032-sysctrl.h index 066dfb15cbdd..25542b49eb55 100644 --- a/include/linux/soc/renesas/r9a06g032-sysctrl.h +++ b/include/linux/soc/renesas/r9a06g032-sysctrl.h @@ -4,8 +4,20 @@ =20 #ifdef CONFIG_CLK_R9A06G032 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val); + +enum r9a06g032_sysctrl_rst_src { + R9A06G032_RST_WATCHDOG_CA7_0, + R9A06G032_RST_WATCHDOG_CA7_1, +}; + +int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src); + #else static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return= -ENODEV; } +static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_= src rst_src) +{ + return -ENODEV; +} #endif =20 #endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__ */ --=20 2.53.0