Introduce support for the Mahua SoC and the CRD based on it. Some of
the notable differences are the absent CPU cluster, interconnect, TLMM,
thermal zones and adjusted PCIe west clocks. Everything else should
work as-is.
Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
6 files changed, 1066 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 317af937d038..e85ff36012f1 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb
lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index e269cec7942c..4e0b44af073e 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -282,7 +282,7 @@ core5 {
};
};
- cluster2 {
+ cpu_map_cluster2: cluster2 {
core0 {
cpu = <&cpu12>;
};
diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts
new file mode 100644
index 000000000000..9c8244e892dd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "mahua.dtsi"
+#include "glymur-crd.dtsi"
+
+/delete-node/ &pmcx0102_d_e0;
+/delete-node/ &pmcx0102_d0_thermal;
+/delete-node/ &pmh0104_i_e0;
+/delete-node/ &pmh0104_i0_thermal;
+/delete-node/ &pmh0104_j_e0;
+/delete-node/ &pmh0104_j0_thermal;
+
+/ {
+ model = "Qualcomm Technologies, Inc. Mahua CRD";
+ compatible = "qcom,mahua-crd", "qcom,mahua";
+};
diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
new file mode 100644
index 000000000000..893b3a721bc6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
@@ -0,0 +1,1040 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/* Mahua is heavily based on Glymur, with some meaningful differences */
+#include "glymur.dtsi"
+
+/delete-node/ &cluster2_pd;
+/delete-node/ &cpu_map_cluster2;
+/delete-node/ &cpu12;
+/delete-node/ &cpu13;
+/delete-node/ &cpu14;
+/delete-node/ &cpu15;
+/delete-node/ &cpu16;
+/delete-node/ &cpu17;
+/delete-node/ &cpu_pd12;
+/delete-node/ &cpu_pd13;
+/delete-node/ &cpu_pd14;
+/delete-node/ &cpu_pd15;
+/delete-node/ &cpu_pd16;
+/delete-node/ &cpu_pd17;
+/delete-node/ &thermal_zones;
+/delete-node/ &tsens6;
+/delete-node/ &tsens7;
+
+&aggre1_noc {
+ compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc";
+};
+
+&aggre2_noc {
+ compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc";
+};
+
+&aggre3_noc {
+ compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc";
+};
+
+&aggre4_noc {
+ compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc";
+};
+
+&clk_virt {
+ compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt";
+};
+
+&cnoc_main {
+ compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main";
+};
+
+&config_noc {
+ compatible = "qcom,mahua-cnoc-cfg";
+};
+
+&hsc_noc {
+ compatible = "qcom,mahua-hscnoc";
+};
+
+&lpass_ag_noc {
+ compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc";
+};
+
+&lpass_lpiaon_noc {
+ compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc";
+};
+
+&lpass_lpicx_noc {
+ compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc";
+};
+
+&mc_virt {
+ compatible = "qcom,mahua-mc-virt";
+};
+
+&mmss_noc {
+ compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc";
+};
+
+&nsi_noc {
+ compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc";
+};
+
+&nsp_noc {
+ compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc";
+};
+
+&oobm_ss_noc {
+ compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
+};
+
+&pcie_east_anoc {
+ compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
+};
+
+&pcie_east_slv_noc {
+ compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc";
+};
+
+&pcie_west_anoc {
+ compatible = "qcom,mahua-pcie-west-anoc";
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
+};
+
+&pcie_west_slv_noc {
+ compatible = "qcom,mahua-pcie-west-slv-noc";
+};
+
+&system_noc {
+ compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc";
+};
+
+&tlmm {
+ compatible = "qcom,mahua-tlmm";
+};
+
+&tsens4 {
+ #qcom,sensors = <13>;
+};
+
+&tsens5 {
+ #qcom,sensors = <15>;
+};
+
+/ {
+ thermal_zones: thermal-zones {
+ aoss-0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu-0-0-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu-0-0-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu-0-1-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu-0-1-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpu-0-2-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-1-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpu-0-2-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-0-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu-0-3-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-1-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu-0-3-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-0-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu-0-4-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-1-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu-0-4-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-0-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu-0-5-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-1-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu-0-5-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-0-thermal {
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ cpullc-0-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-1-thermal {
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ cpullc-0-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-0-thermal {
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ qmx-0-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-1-thermal {
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ qmx-0-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-2-thermal {
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ qmx-0-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-0-thermal {
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ ddr-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-1-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ ddr-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-0-thermal {
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ video-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-2-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ aoss-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-0-thermal {
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ cpu-1-0-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-1-thermal {
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ cpu-1-0-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-0-thermal {
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ cpu-1-1-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-1-thermal {
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ cpu-1-1-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-0-thermal {
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ cpu-1-2-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-1-thermal {
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ cpu-1-2-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-0-thermal {
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ cpu-1-3-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-1-thermal {
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ cpu-1-3-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-4-0-thermal {
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ cpu-1-4-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-4-1-thermal {
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ cpu-1-4-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-5-0-thermal {
+ thermal-sensors = <&tsens2 11>;
+
+ trips {
+ cpu-1-5-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-5-1-thermal {
+ thermal-sensors = <&tsens2 12>;
+
+ trips {
+ cpu-1-5-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-3-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ aoss-3-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-0-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ cpullc-1-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-1-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ cpullc-1-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-0-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ qmx-1-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-1-thermal {
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ qmx-1-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-2-thermal {
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ qmx-1-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-3-thermal {
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ qmx-1-3-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-4-thermal {
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ qmx-1-4-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-4-thermal {
+ thermal-sensors = <&tsens4 0>;
+
+ trips {
+ aoss-4-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-0-thermal {
+ thermal-sensors = <&tsens4 1>;
+
+ trips {
+ nsphvx-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-1-thermal {
+ thermal-sensors = <&tsens4 2>;
+
+ trips {
+ nsphvx-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-2-thermal {
+ thermal-sensors = <&tsens4 3>;
+
+ trips {
+ nsphvx-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-3-thermal {
+ thermal-sensors = <&tsens4 4>;
+
+ trips {
+ nsphvx-3-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-0-thermal {
+ thermal-sensors = <&tsens4 5>;
+
+ trips {
+ nsphmx-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-1-thermal {
+ thermal-sensors = <&tsens4 6>;
+
+ trips {
+ nsphmx-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-2-thermal {
+ thermal-sensors = <&tsens4 7>;
+
+ trips {
+ nsphmx-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-3-thermal {
+ thermal-sensors = <&tsens4 8>;
+
+ trips {
+ nsphmx-3-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-0-thermal {
+ thermal-sensors = <&tsens4 9>;
+
+ trips {
+ camera-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-1-thermal {
+ thermal-sensors = <&tsens4 10>;
+
+ trips {
+ camera-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-5-thermal {
+ thermal-sensors = <&tsens5 0>;
+
+ trips {
+ aoss-5-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-0-thermal {
+ thermal-sensors = <&tsens5 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-1-thermal {
+ thermal-sensors = <&tsens5 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-2-thermal {
+ thermal-sensors = <&tsens5 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-0-thermal {
+ thermal-sensors = <&tsens5 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-1-thermal {
+ thermal-sensors = <&tsens5 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-2-thermal {
+ thermal-sensors = <&tsens5 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-0-thermal {
+ thermal-sensors = <&tsens5 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-1-thermal {
+ thermal-sensors = <&tsens5 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-2-thermal {
+ thermal-sensors = <&tsens5 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ thermal-sensors = <&tsens5 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-0-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ thermal-sensors = <&tsens5 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-1-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-2-thermal {
+ thermal-sensors = <&tsens5 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-2-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-3-thermal {
+ thermal-sensors = <&tsens5 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-3-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-4-thermal {
+ thermal-sensors = <&tsens5 14>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-4-critical {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
index c3ccd2b75609..db2da9ef4f01 100644
--- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
@@ -46,7 +46,7 @@ trip1 {
};
};
- pmcx0102-d0-thermal {
+ pmcx0102_d0_thermal: pmcx0102-d0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
index d89cceda53a3..7a1e5f355c17 100644
--- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
@@ -8,7 +8,7 @@
/{
thermal_zones {
- pmh0104-i0-thermal {
+ pmh0104_i0_thermal: pmh0104-i0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
@@ -27,7 +27,7 @@ trip1 {
};
};
- pmh0104-j0-thermal {
+ pmh0104_j0_thermal: pmh0104-j0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_j_e0_temp_alarm>;
--
2.34.1On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote:
> Introduce support for the Mahua SoC and the CRD based on it. Some of
> the notable differences are the absent CPU cluster, interconnect, TLMM,
> thermal zones and adjusted PCIe west clocks. Everything else should
> work as-is.
>
> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
> arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
> 6 files changed, 1066 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
> create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
>
> +
> +&tsens4 {
> + #qcom,sensors = <13>;
This matches the value in glymur.dtsi
> +};
> +
> +&tsens5 {
> + #qcom,sensors = <15>;
This one is indeed different.
> +};
> +
> +/ {
> + thermal_zones: thermal-zones {
You've completely rewritten thermal zones. Can we patch them instead?
The difference would be more obvious this way.
--
With best wishes
Dmitry
On 3/12/26 4:02 AM, Dmitry Baryshkov wrote:
> On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote:
>> Introduce support for the Mahua SoC and the CRD based on it. Some of
>> the notable differences are the absent CPU cluster, interconnect, TLMM,
>> thermal zones and adjusted PCIe west clocks. Everything else should
>> work as-is.
>>
>> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
>> arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
>> arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
>> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
>> 6 files changed, 1066 insertions(+), 4 deletions(-)
>> create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
>>
>> +
>> +&tsens4 {
>> + #qcom,sensors = <13>;
>
> This matches the value in glymur.dtsi
>
>> +};
>> +
>> +&tsens5 {
>> + #qcom,sensors = <15>;
>
> This one is indeed different.
>
>> +};
>> +
>> +/ {
>> + thermal_zones: thermal-zones {
>
> You've completely rewritten thermal zones. Can we patch them instead?
It's more messy that way, sensors are reassigned because there's less of
them (and less things to monitor)
Konrad
On Fri, Mar 13, 2026 at 11:06:46AM +0100, Konrad Dybcio wrote:
> On 3/12/26 4:02 AM, Dmitry Baryshkov wrote:
> > On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote:
> >> Introduce support for the Mahua SoC and the CRD based on it. Some of
> >> the notable differences are the absent CPU cluster, interconnect, TLMM,
> >> thermal zones and adjusted PCIe west clocks. Everything else should
> >> work as-is.
> >>
> >> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> >> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> >> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> >> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> >> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/Makefile | 1 +
> >> arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
> >> arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
> >> arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
> >> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
> >> 6 files changed, 1066 insertions(+), 4 deletions(-)
> >> create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
> >> create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
> >>
> >> +
> >> +&tsens4 {
> >> + #qcom,sensors = <13>;
> >
> > This matches the value in glymur.dtsi
> >
> >> +};
> >> +
> >> +&tsens5 {
> >> + #qcom,sensors = <15>;
> >
> > This one is indeed different.
> >
> >> +};
> >> +
> >> +/ {
> >> + thermal_zones: thermal-zones {
> >
> > You've completely rewritten thermal zones. Can we patch them instead?
>
> It's more messy that way, sensors are reassigned because there's less of
> them (and less things to monitor)
I'd say, it's a bit messy either way.
--
With best wishes
Dmitry
Hi Dmitry,
On 3/12/2026 8:32 AM, Dmitry Baryshkov wrote:
> On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote:
>> Introduce support for the Mahua SoC and the CRD based on it. Some of
>> the notable differences are the absent CPU cluster, interconnect, TLMM,
>> thermal zones and adjusted PCIe west clocks. Everything else should
>> work as-is.
>>
>> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
>> arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
>> arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
>> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
>> 6 files changed, 1066 insertions(+), 4 deletions(-)
>> create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
>>
>> +
>> +&tsens4 {
>> + #qcom,sensors = <13>;
>
> This matches the value in glymur.dtsi
my bad, it is supposed to be 11 for mahua. It is taken care in below
thermal zone list. Will update in next revision.
>
>> +};
>> +
>> +&tsens5 {
>> + #qcom,sensors = <15>;
>
> This one is indeed different.
>
>> +};
>> +
>> +/ {
>> + thermal_zones: thermal-zones {
>
> You've completely rewritten thermal zones. Can we patch them instead?
> The difference would be more obvious this way.
Out of the 69 sensors in Mahua, around 27 sensors show discrepancies
when compared with Glymur. These differences are not limited to sensor
ID updates alone; due to changes in sensor mapping, some nodes trip and
cooling binding require node-level updates.
Additionally, approximately 23 thermal zone sensor nodes need to be
deleted individually, since Glymur has a total of 92 sensors.
Considering this, would it be better to delete the entire set of thermal
zones and reconfigure them specifically for Mahua to improve clarity and
maintainability? I noticed that Purwa followed a similar approach.
Thanks,
Manaf
>
>
On Fri, Mar 13, 2026 at 12:38:04PM +0530, Manaf Meethalavalappu Pallikunhi wrote:
> Hi Dmitry,
>
>
> On 3/12/2026 8:32 AM, Dmitry Baryshkov wrote:
> > On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote:
> > > Introduce support for the Mahua SoC and the CRD based on it. Some of
> > > the notable differences are the absent CPU cluster, interconnect, TLMM,
> > > thermal zones and adjusted PCIe west clocks. Everything else should
> > > work as-is.
> > >
> > > Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> > > Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> > > Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> > > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> > > Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/Makefile | 1 +
> > > arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
> > > arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 +
> > > arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++
> > > arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +-
> > > arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +-
> > > 6 files changed, 1066 insertions(+), 4 deletions(-)
> > > create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
> > > create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi
> > >
> > > +
> > > +&tsens4 {
> > > + #qcom,sensors = <13>;
> >
> > This matches the value in glymur.dtsi
>
> my bad, it is supposed to be 11 for mahua. It is taken care in below thermal
> zone list. Will update in next revision.
Good :-)
And now you see the importance of it being a patch rather than a
complete thermel zone drop. It is easy to review diff.
> >
> > > +};
> > > +
> > > +&tsens5 {
> > > + #qcom,sensors = <15>;
> >
> > This one is indeed different.
> >
> > > +};
> > > +
> > > +/ {
> > > + thermal_zones: thermal-zones {
> >
> > You've completely rewritten thermal zones. Can we patch them instead?
> > The difference would be more obvious this way.
>
> Out of the 69 sensors in Mahua, around 27 sensors show discrepancies when
> compared with Glymur. These differences are not limited to sensor ID updates
> alone; due to changes in sensor mapping, some nodes trip and cooling binding
> require node-level updates.
> Additionally, approximately 23 thermal zone sensor nodes need to be deleted
> individually, since Glymur has a total of 92 sensors.
> Considering this, would it be better to delete the entire set of thermal
> zones and reconfigure them specifically for Mahua to improve clarity and
> maintainability? I noticed that Purwa followed a similar approach.
I will take a look at Purwa, maybe submitting a fix.
>
> Thanks,
> Manaf
>
> >
> >
>
--
With best wishes
Dmitry
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