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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-41756d4c581sm1487020fac.10.2026.03.09.22.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 22:50:44 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, Gopikrishna Garmidi , Raviteja Laggyshetty , Kamal Wadhwa , Manaf Meethalavalappu Pallikunhi Subject: [PATCH 3/3] arm64: dts: qcom: Add Mahua SoC and CRD Date: Mon, 9 Mar 2026 22:49:47 -0700 Message-Id: <20260310054947.2114445-4-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Rcmdyltv c=1 sm=1 tr=0 ts=69afb136 cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=3Evy3uxcNZOedNsqlpQA:9 a=efpaJB4zofY2dbm2aIRb:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDA0NiBTYWx0ZWRfX80DVNOzvh+OX rgXYMp6uROKEHrL4w0v7VKl40Q1LNasRArkVcKW4TObFRddDxApnsnAnlX6cQ/Ksa9hIKqJ4V0p jYUzv7CMGcPTFQIZxA6ClMrHDrJ3+ttdntjUh7vtTfkYJ4rFZ0GslDuPUxRT5Uw9lSlTafh5VDM FSTSo7yM0A6SKVQnWCZVNKK8CWPJuCm+3j0tVln62RCpQ+WRpgTFJ0UppZkVefXBkyF6d0hZNJs z/CF+wpBBLpgcEiW67VYbwKx49k/xvAnALuCiCelIbURIDm6UGqz6gEffukN63aDzPawrTkdA3b PSw2VsISzdLIpeC/bhnsi4LxEBMNuw9p+roDUxA6YSQWamGJalIhKTAhFHbr1PfqulxFSUwRUCO vpueSpNLTbIgj1VgoEW0RIxbsWmbaOgVYmjATqCleF5dPaZaw//e2/tu0fQ965SJcKD1MccoQ1e pvCKKzEL1OszDeJenlw== X-Proofpoint-GUID: X8ac9eCRx8PrvUU8CMY92qzk6cCGHQsM X-Proofpoint-ORIG-GUID: X8ac9eCRx8PrvUU8CMY92qzk6cCGHQsM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100046 Content-Type: text/plain; charset="utf-8" Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gopikrishna Garmidi --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 + arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- 6 files changed, 1066 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 317af937d038..e85ff36012f1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..4e0b44af073e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -282,7 +282,7 @@ core5 { }; }; =20 - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu =3D <&cpu12>; }; diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts new file mode 100644 index 000000000000..9c8244e892dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model =3D "Qualcomm Technologies, Inc. Mahua CRD"; + compatible =3D "qcom,mahua-crd", "qcom,mahua"; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi new file mode 100644 index 000000000000..893b3a721bc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,1040 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &thermal_zones; +/delete-node/ &tsens6; +/delete-node/ &tsens7; + +&aggre1_noc { + compatible =3D "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible =3D "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible =3D "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible =3D "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible =3D "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible =3D "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible =3D "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible =3D "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible =3D "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible =3D "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-n= oc"; +}; + +&lpass_lpicx_noc { + compatible =3D "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc= "; +}; + +&mc_virt { + compatible =3D "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible =3D "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible =3D "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible =3D "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible =3D "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv= -noc"; +}; + +&pcie_west_anoc { + compatible =3D "qcom,mahua-pcie-west-anoc"; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible =3D "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible =3D "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&tlmm { + compatible =3D "qcom,mahua-tlmm"; +}; + +&tsens4 { + #qcom,sensors =3D <13>; +}; + +&tsens5 { + #qcom,sensors =3D <15>; +}; + +/ { + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors =3D <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors =3D <&tsens1 6>; + + trips { + ddr-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-1-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + ddr-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-0-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + video-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + aoss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors =3D <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors =3D <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors =3D <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors =3D <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors =3D <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors =3D <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors =3D <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + aoss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors =3D <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors =3D <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors =3D <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors =3D <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + aoss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + nsphvx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + nsphvx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + nsphvx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + nsphvx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + nsphmx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + nsphmx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + nsphmx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 8>; + + trips { + nsphmx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens4 9>; + + trips { + camera-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens4 10>; + + trips { + camera-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + aoss-5-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens5 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens5 9>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 10>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/q= com/pmcx0102.dtsi index c3ccd2b75609..db2da9ef4f01 100644 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; =20 - pmcx0102-d0-thermal { + pmcx0102_d0_thermal: pmcx0102-d0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmcx0102_d_e0_temp_alarm>; =20 diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0104-glymur.dtsi index d89cceda53a3..7a1e5f355c17 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -8,7 +8,7 @@ =20 /{ thermal_zones { - pmh0104-i0-thermal { + pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_i_e0_temp_alarm>; =20 @@ -27,7 +27,7 @@ trip1 { }; }; =20 - pmh0104-j0-thermal { + pmh0104_j0_thermal: pmh0104-j0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_j_e0_temp_alarm>; =20 --=20 2.34.1