Mahua is a variant of Glymur with the same silicon but with the
third CPU cluster (CPUs 12-17) disabled.

Introduce the DTS bits required for Mahua SoC and the CRD based on it.
Some of the notable differences are the absent CPU cluster, interconnect,
TLMM, thermal zones and adjusted PCIe west clocks. Everything else should
work as-is.

Gopikrishna Garmidi (3):
  dt-bindings: arm: qcom: Document Mahua SoC and board
  arm64: dts: qcom: Commonize Glymur CRD DTSI
  arm64: dts: qcom: Add Mahua SoC and CRD

 .../devicetree/bindings/arm/qcom.yaml         |    5 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/glymur-crd.dts       |  586 +---------
 .../qcom/{glymur-crd.dts => glymur-crd.dtsi}  |    7 -
 arch/arm64/boot/dts/qcom/glymur.dtsi          |    2 +-
 arch/arm64/boot/dts/qcom/mahua-crd.dts        |   21 +
 arch/arm64/boot/dts/qcom/mahua.dtsi           | 1040 +++++++++++++++++
 arch/arm64/boot/dts/qcom/pmcx0102.dtsi        |    2 +-
 arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi  |    4 +-
 9 files changed, 1072 insertions(+), 596 deletions(-)
 copy arch/arm64/boot/dts/qcom/{glymur-crd.dts => glymur-crd.dtsi} (99%)
 create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts
 create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi


base-commit: 3ef088b0c5772a6f75634e54aa34f5fc0a2c041c
prerequisite-message-id: <20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com>
-- 
2.34.1