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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-41756d4c581sm1487020fac.10.2026.03.09.22.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 22:50:36 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, Gopikrishna Garmidi Subject: [PATCH 1/3] dt-bindings: arm: qcom: Document Mahua SoC and board Date: Mon, 9 Mar 2026 22:49:45 -0700 Message-Id: <20260310054947.2114445-2-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDA0NiBTYWx0ZWRfX7ZIuzamEuRuY 5Oa/Ei1Eoj6rxOE1eCLoisix9PElRzuU3l7KhCExpsxsAJGKKLPHDHHi5+lFrBObQoHQTENUTrB tlj62P8+WfxSBrxNTOEqfpzvsx0/CepnqKM0HO5+67vmCJsEe/GPLj/rM/gI8y0rSRSeLW0BzE1 wG2FO05OfDBxRjRjixYLwGLZsoibE7gxIN9yzAia+dXSfHmjNlgHtVwBbgmbN53Ya2OURCy2oAh uNt52b+X8CRUSzBJli4+EwGvzDEougD+cBO5poTW/QJekmYlfCL2wdFdFllWX29Vz0zbVVCqfu9 28E5byh+D+n56yb0SLfhBycsCABl714kQ6zqC4Sjpd6biVOfAAZ4r31NekWh7JpcSKmxmdBmPVG LTeOAMPB1PxfvpBlvTZ2v2gC62czitfhQcv11gBw1LK2SKVFzQB9wqpbmq6hG7QZvPFVj5otQnW nn1RQqK9iIM6GkCdadA== X-Authority-Analysis: v=2.4 cv=OcmVzxTY c=1 sm=1 tr=0 ts=69afb12d cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=QEbT8_BQrpgYwvZUqSkA:9 a=efpaJB4zofY2dbm2aIRb:22 X-Proofpoint-GUID: XCeGmPvCj31v5cfF3dAlrFH15P4CZDbX X-Proofpoint-ORIG-GUID: XCeGmPvCj31v5cfF3dAlrFH15P4CZDbX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100046 Content-Type: text/plain; charset="utf-8" Mahua is a derivative of Glymur with the third CPU cluster disabled. Document the compatible strings for the Mahua SoC and the Compute Reference Device (CRD) board based on it. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 34a19e664556..be104b4be7a0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -66,6 +66,11 @@ properties: - qcom,glymur-crd - const: qcom,glymur =20 + - items: + - enum: + - qcom,mahua-crd + - const: qcom,mahua + - items: - enum: - fairphone,fp6 --=20 2.34.1 From nobody Thu Apr 9 08:09:43 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 057303C199D for ; Tue, 10 Mar 2026 05:50:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-41756d4c581sm1487020fac.10.2026.03.09.22.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 22:50:40 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, Gopikrishna Garmidi Subject: [PATCH 2/3] arm64: dts: qcom: Commonize Glymur CRD DTSI Date: Mon, 9 Mar 2026 22:49:46 -0700 Message-Id: <20260310054947.2114445-3-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDA0NiBTYWx0ZWRfX17h75nUIOYIa Invk4Ke4aZ1jkX5rM6+kUbtch5DkYeG+x7pMlURkZrZzp/gHzeXkToA254yL5e45iHIz+IC4Zbs MRyIYvmO1pMiAbfJI5CPew1pA8M1ukDzWdDaNxDA+gC8z8y7IAKpoqj57aFI5RNoOzO6FcyOcHE 40U8/X49RBtyA4JMzWgRxP3TN2VdkBuzkv5fZGGtbAXgNeKvjkzIMWI553JyOV11EPZ6DG3oAXp o/6imELrxTWCuvc9J4Qa5YXV7yQiubdFhK4AXo7dOOaRhTr6JdzQpeN+IZJm7+tXcHLwNIsnc3k Z8VOY/WlNa5gY9GG2GXSY3yVKjZf4qac+pxveH13emWvAPPy/KUkfQ48onm/mchknLctljmPD3J EMP10EEpeb8FVHs9W47WfmhC3w+1LlnzMi5HnfzQzM0ATx4wjxLpAxmGS1QyeUBswIhor7eTtBf BcSXwIuwR3g0upgNdqw== X-Proofpoint-GUID: tTcDY5Xnaz270KOI64YVJXpwbnIHeJet X-Authority-Analysis: v=2.4 cv=Jtf8bc4C c=1 sm=1 tr=0 ts=69afb131 cx=c_pps a=nSjmGuzVYOmhOUYzIAhsAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=Lx9aQ9xY3w96JebXmp4A:9 a=1zu1i0D7hVQfj8NKfPKu:22 X-Proofpoint-ORIG-GUID: tTcDY5Xnaz270KOI64YVJXpwbnIHeJet X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100046 Content-Type: text/plain; charset="utf-8" Commonize the existing Glymur DTSI to allow reuse across the different Glymur SKUs. Also leave PCIe3b nodes disabled until the PCIe3b PHY init sequence support gets added, since it's disabled at the UEFI level by default. Signed-off-by: Gopikrishna Garmidi --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 586 +----------------- .../qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} | 7 - 2 files changed, 1 insertion(+), 592 deletions(-) copy arch/arm64/boot/dts/qcom/{glymur-crd.dts =3D> glymur-crd.dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 877945319012..0efd9e27c82f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -6,593 +6,9 @@ /dts-v1/; =20 #include "glymur.dtsi" -#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ -#include "pmh0101.dtsi" /* SPMI0: SID-1 */ -#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ -#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ -#include "pmk8850.dtsi" /* SPMI0: SID-0 */ -#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ +#include "glymur-crd.dtsi" =20 / { model =3D "Qualcomm Technologies, Inc. Glymur CRD"; compatible =3D "qcom,glymur-crd", "qcom,glymur"; - - aliases { - serial0 =3D &uart21; - serial1 =3D &uart14; - i2c0 =3D &i2c0; - i2c1 =3D &i2c4; - i2c2 =3D &i2c5; - spi0 =3D &spi18; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - clocks { - xo_board: xo-board { - compatible =3D "fixed-clock"; - clock-frequency =3D <38400000>; - #clock-cells =3D <0>; - }; - - sleep_clk: sleep-clk { - compatible =3D "fixed-clock"; - clock-frequency =3D <32000>; - #clock-cells =3D <0>; - }; - }; - - gpio-keys { - compatible =3D "gpio-keys"; - - pinctrl-0 =3D <&key_vol_up_default>; - pinctrl-names =3D "default"; - - key-volume-up { - label =3D "Volume Up"; - linux,code =3D ; - gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval =3D <15>; - linux,can-disable; - wakeup-source; - }; - }; - - vreg_nvme: regulator-nvme { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_nvmesec: regulator-nvmesec { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_NVME_SEC_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&nvme_sec_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wlan: regulator-wlan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WLAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wlan_reg_en>; - pinctrl-names =3D "default"; - - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible =3D "regulator-fixed"; - - regulator-name =3D "VREG_WWAN_3P3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - - gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 =3D <&wwan_reg_en>; - pinctrl-names =3D "default"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible =3D "qcom,pmh0101-rpmh-regulators"; - qcom,pmic-id =3D "B_E0"; - - vreg_bob1_e0: bob1 { - regulator-name =3D "vreg_bob1_e0"; - regulator-min-microvolt =3D <2200000>; - regulator-max-microvolt =3D <4224000>; - regulator-initial-mode =3D ; - }; - - vreg_bob2_e0: bob2 { - regulator-name =3D "vreg_bob2_e0"; - regulator-min-microvolt =3D <2540000>; - regulator-max-microvolt =3D <3600000>; - regulator-initial-mode =3D ; - }; - - vreg_l1b_e0_1p8: ldo1 { - regulator-name =3D "vreg_l1b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l2b_e0_2p9: ldo2 { - regulator-name =3D "vreg_l2b_e0_2p9"; - regulator-min-microvolt =3D <2904000>; - regulator-max-microvolt =3D <2904000>; - regulator-initial-mode =3D ; - }; - - vreg_l7b_e0_2p79: ldo7 { - regulator-name =3D "vreg_l7b_e0_2p79"; - regulator-min-microvolt =3D <2790000>; - regulator-max-microvolt =3D <2792000>; - regulator-initial-mode =3D ; - }; - - vreg_l8b_e0_1p50: ldo8 { - regulator-name =3D "vreg_l8b_e0_1p50"; - regulator-min-microvolt =3D <1504000>; - regulator-max-microvolt =3D <1504000>; - regulator-initial-mode =3D ; - }; - - vreg_l9b_e0_2p7: ldo9 { - regulator-name =3D "vreg_l9b_e0_2p7"; - regulator-min-microvolt =3D <2704000>; - regulator-max-microvolt =3D <2704000>; - regulator-initial-mode =3D ; - }; - - vreg_l10b_e0_1p8: ldo10 { - regulator-name =3D "vreg_l10b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l11b_e0_1p2: ldo11 { - regulator-name =3D "vreg_l11b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l12b_e0_1p14: ldo12 { - regulator-name =3D "vreg_l12b_e0_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l15b_e0_1p8: ldo15 { - regulator-name =3D "vreg_l15b_e0_1p8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_l17b_e0_2p4: ldo17 { - regulator-name =3D "vreg_l17b_e0_2p4"; - regulator-min-microvolt =3D <2400000>; - regulator-max-microvolt =3D <2700000>; - regulator-initial-mode =3D ; - }; - - vreg_l18b_e0_1p2: ldo18 { - regulator-name =3D "vreg_l18b_e0_1p2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-1 { - compatible =3D "qcom,pmcx0102-rpmh-regulators"; - qcom,pmic-id =3D "C_E1"; - - vreg_l1c_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1c_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2c_e1_1p14: ldo2 { - regulator-name =3D "vreg_l2c_e1_1p14"; - regulator-min-microvolt =3D <1144000>; - regulator-max-microvolt =3D <1144000>; - regulator-initial-mode =3D ; - }; - - vreg_l3c_e1_0p89: ldo3 { - regulator-name =3D "vreg_l3c_e1_0p89"; - regulator-min-microvolt =3D <890000>; - regulator-max-microvolt =3D <980000>; - regulator-initial-mode =3D ; - }; - - vreg_l4c_e1_0p72: ldo4 { - regulator-name =3D "vreg_l4c_e1_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-2 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E0"; - - vreg_s7f_e0_1p32: smps7 { - regulator-name =3D "vreg_s7f_e0_1p32"; - regulator-min-microvolt =3D <1320000>; - regulator-max-microvolt =3D <1352000>; - regulator-initial-mode =3D ; - }; - - vreg_s8f_e0_0p95: smps8 { - regulator-name =3D "vreg_s8f_e0_0p95"; - regulator-min-microvolt =3D <952000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_s9f_e0_1p9: smps9 { - regulator-name =3D "vreg_s9f_e0_1p9"; - regulator-min-microvolt =3D <1900000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e0_0p82: ldo2 { - regulator-name =3D "vreg_l2f_e0_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3f_e0_0p72: ldo3 { - regulator-name =3D "vreg_l3f_e0_0p72"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <720000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e0_0p3: ldo4 { - regulator-name =3D "vreg_l4f_e0_0p3"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-3 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "F_E1"; - - vreg_s7f_e1_0p3: smps7 { - regulator-name =3D "vreg_s7f_e1_0p3"; - regulator-min-microvolt =3D <300000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - }; - - vreg_l1f_e1_0p82: ldo1 { - regulator-name =3D "vreg_l1f_e1_0p82"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2f_e1_0p83: ldo2 { - regulator-name =3D "vreg_l2f_e1_0p83"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l4f_e1_1p08: ldo4 { - regulator-name =3D "vreg_l4f_e1_1p08"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; - - regulators-4 { - compatible =3D "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id =3D "H_E0"; - - vreg_l1h_e0_0p89: ldo1 { - regulator-name =3D "vreg_l1h_e0_0p89"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l2h_e0_0p72: ldo2 { - regulator-name =3D "vreg_l2h_e0_0p72"; - regulator-min-microvolt =3D <832000>; - regulator-max-microvolt =3D <832000>; - regulator-initial-mode =3D ; - }; - - vreg_l3h_e0_0p32: ldo3 { - regulator-name =3D "vreg_l3h_e0_0p32"; - regulator-min-microvolt =3D <320000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - }; - - vreg_l4h_e0_1p2: ldo4 { - regulator-name =3D "vreg_l4h_e0_1p2"; - regulator-min-microvolt =3D <1080000>; - regulator-max-microvolt =3D <1320000>; - regulator-initial-mode =3D ; - }; - }; -}; - -&pcie3b { - vddpe-3v3-supply =3D <&vreg_nvmesec>; - - pinctrl-0 =3D <&pcie3b_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie3b_phy { - vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; - vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; - - status =3D "okay"; -}; - -&pcie3b_port0 { - reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; -}; - -&pcie4 { - vddpe-3v3-supply =3D <&vreg_wlan>; - - pinctrl-0 =3D <&pcie4_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie4_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie4_port0 { - reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; -}; - -&pcie5 { - vddpe-3v3-supply =3D <&vreg_nvme>; - - pinctrl-0 =3D <&pcie5_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie5_phy { - vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; - vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; - - status =3D "okay"; -}; - -&pcie5_port0 { - reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pcie6 { - vddpe-3v3-supply =3D <&vreg_wwan>; - - pinctrl-0 =3D <&pcie6_default>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&pcie6_phy { - vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; - vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; - - status =3D "okay"; -}; - -&pcie6_port0 { - reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; -}; - -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0110_f_e1_gpios { - nvme_sec_reg_en: nvme-reg-en-state { - pins =3D "gpio14"; - function =3D "normal"; - bias-disable; - }; -}; - -&pmh0101_gpios { - key_vol_up_default: key-vol-up-default-state { - pins =3D "gpio6"; - function =3D "normal"; - output-disable; - bias-pull-up; - }; -}; - -&pmk8850_rtc { - qcom,no-alarm; -}; - -&pon_resin { - linux,code =3D ; - status =3D "okay"; -}; - -&tlmm { - gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ - <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins =3D "gpio147"; - function =3D "pcie4_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio146"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio148"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins =3D "gpio153"; - function =3D "pcie5_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio152"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio154"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie6_default: pcie6-default-state { - clkreq-n-pins { - pins =3D "gpio150"; - function =3D "pcie6_clk_req_n"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio149"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio151"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie3b_default: pcie3b-default-state { - clkreq-n-pins { - pins =3D "gpio156"; - function =3D "pcie3b_clk"; - drive-strength =3D <2>; - bias-pull-up; - }; - - perst-n-pins { - pins =3D "gpio155"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wake-n-pins { - pins =3D "gpio157"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - wlan_reg_en: wlan-reg-en-state { - pins =3D "gpio94"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; - - wwan_reg_en: wwan-reg-en-state { - pins =3D "gpio246"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dtsi similarity index 99% copy from arch/arm64/boot/dts/qcom/glymur-crd.dts copy to arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 877945319012..abc6cc8bb0a8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -3,9 +3,6 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 -/dts-v1/; - -#include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ #include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ @@ -372,15 +369,11 @@ &pcie3b { =20 pinctrl-0 =3D <&pcie3b_default>; pinctrl-names =3D "default"; - - status =3D "okay"; }; =20 &pcie3b_phy { vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-41756d4c581sm1487020fac.10.2026.03.09.22.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 22:50:44 -0700 (PDT) From: Gopikrishna Garmidi To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, Gopikrishna Garmidi , Raviteja Laggyshetty , Kamal Wadhwa , Manaf Meethalavalappu Pallikunhi Subject: [PATCH 3/3] arm64: dts: qcom: Add Mahua SoC and CRD Date: Mon, 9 Mar 2026 22:49:47 -0700 Message-Id: <20260310054947.2114445-4-gopikrishna.garmidi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> References: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Rcmdyltv c=1 sm=1 tr=0 ts=69afb136 cx=c_pps a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=3Evy3uxcNZOedNsqlpQA:9 a=efpaJB4zofY2dbm2aIRb:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDA0NiBTYWx0ZWRfX80DVNOzvh+OX rgXYMp6uROKEHrL4w0v7VKl40Q1LNasRArkVcKW4TObFRddDxApnsnAnlX6cQ/Ksa9hIKqJ4V0p jYUzv7CMGcPTFQIZxA6ClMrHDrJ3+ttdntjUh7vtTfkYJ4rFZ0GslDuPUxRT5Uw9lSlTafh5VDM FSTSo7yM0A6SKVQnWCZVNKK8CWPJuCm+3j0tVln62RCpQ+WRpgTFJ0UppZkVefXBkyF6d0hZNJs z/CF+wpBBLpgcEiW67VYbwKx49k/xvAnALuCiCelIbURIDm6UGqz6gEffukN63aDzPawrTkdA3b PSw2VsISzdLIpeC/bhnsi4LxEBMNuw9p+roDUxA6YSQWamGJalIhKTAhFHbr1PfqulxFSUwRUCO vpueSpNLTbIgj1VgoEW0RIxbsWmbaOgVYmjATqCleF5dPaZaw//e2/tu0fQ965SJcKD1MccoQ1e pvCKKzEL1OszDeJenlw== X-Proofpoint-GUID: X8ac9eCRx8PrvUU8CMY92qzk6cCGHQsM X-Proofpoint-ORIG-GUID: X8ac9eCRx8PrvUU8CMY92qzk6cCGHQsM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100046 Content-Type: text/plain; charset="utf-8" Introduce support for the Mahua SoC and the CRD based on it. Some of the notable differences are the absent CPU cluster, interconnect, TLMM, thermal zones and adjusted PCIe west clocks. Everything else should work as-is. Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gopikrishna Garmidi --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 + arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- 6 files changed, 1066 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 317af937d038..e85ff36012f1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..4e0b44af073e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -282,7 +282,7 @@ core5 { }; }; =20 - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu =3D <&cpu12>; }; diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts new file mode 100644 index 000000000000..9c8244e892dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model =3D "Qualcomm Technologies, Inc. Mahua CRD"; + compatible =3D "qcom,mahua-crd", "qcom,mahua"; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi new file mode 100644 index 000000000000..893b3a721bc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,1040 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &thermal_zones; +/delete-node/ &tsens6; +/delete-node/ &tsens7; + +&aggre1_noc { + compatible =3D "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible =3D "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible =3D "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible =3D "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible =3D "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible =3D "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible =3D "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible =3D "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible =3D "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible =3D "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-n= oc"; +}; + +&lpass_lpicx_noc { + compatible =3D "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc= "; +}; + +&mc_virt { + compatible =3D "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible =3D "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible =3D "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible =3D "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible =3D "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv= -noc"; +}; + +&pcie_west_anoc { + compatible =3D "qcom,mahua-pcie-west-anoc"; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible =3D "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible =3D "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&tlmm { + compatible =3D "qcom,mahua-tlmm"; +}; + +&tsens4 { + #qcom,sensors =3D <13>; +}; + +&tsens5 { + #qcom,sensors =3D <15>; +}; + +/ { + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors =3D <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors =3D <&tsens1 6>; + + trips { + ddr-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ddr-1-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + ddr-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-0-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + video-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + aoss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors =3D <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors =3D <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors =3D <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors =3D <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors =3D <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors =3D <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors =3D <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + aoss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors =3D <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors =3D <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors =3D <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors =3D <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + aoss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + nsphvx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + nsphvx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + nsphvx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + nsphvx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + nsphmx-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + nsphmx-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + nsphmx-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 8>; + + trips { + nsphmx-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens4 9>; + + trips { + camera-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors =3D <&tsens4 10>; + + trips { + camera-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + aoss-5-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-0-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-1-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors =3D <&tsens5 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors =3D <&tsens5 9>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpu-2-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 10>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <115000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/q= com/pmcx0102.dtsi index c3ccd2b75609..db2da9ef4f01 100644 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; =20 - pmcx0102-d0-thermal { + pmcx0102_d0_thermal: pmcx0102-d0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmcx0102_d_e0_temp_alarm>; =20 diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot= /dts/qcom/pmh0104-glymur.dtsi index d89cceda53a3..7a1e5f355c17 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -8,7 +8,7 @@ =20 /{ thermal_zones { - pmh0104-i0-thermal { + pmh0104_i0_thermal: pmh0104-i0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_i_e0_temp_alarm>; =20 @@ -27,7 +27,7 @@ trip1 { }; }; =20 - pmh0104-j0-thermal { + pmh0104_j0_thermal: pmh0104-j0-thermal { polling-delay-passive =3D <100>; thermal-sensors =3D <&pmh0104_j_e0_temp_alarm>; =20 --=20 2.34.1