From: Loic Poulain <loic.poulain@oss.qualcomm.com>
The Monaco Monza SoM is a compact computing module that integrates a
Monaco/QCS8300 System on Chip (SoC), along with essential components
optimized for IoT applications. It is designed to be mounted on
carrier boards, enabling the development of complete embedded systems.
The following components are described:
- Fixed S2S 1.8V rail
- PMM8654AU RPMh regulators (PMIC A and PMIC C)
- Display subsystem/phy supplies (DSI, DP)
- Enable GPU, GPI DMA, IRIS
- PCIe Gen4 for both controllers and PHY supply hookups
- QUPv3 firmware declarations
- REFGEN always-on workaround for USB2 HS PHY
- Remoteproc firmware names for ADSP, CDSP and GPDSP
- Ethernet SERDES supplies
- USB HS/SS PHY regulators
- On-SoM eMMC
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
---
.../arm64/boot/dts/qcom/monaco-monza-som.dtsi | 325 ++++++++++++++++++
1 file changed, 325 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
new file mode 100644
index 000000000000..9c4f515337de
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "monaco.dtsi"
+#include "monaco-pmics.dtsi"
+
+/ {
+ /* This comes from a PMIC handled within the SAIL domain */
+ vreg_s2s: vreg-s2s {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2s";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmm8654au-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vreg_l3a: ldo3 {
+ regulator-name = "vreg_l3a";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l4a: ldo4 {
+ regulator-name = "vreg_l4a";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a: ldo5 {
+ regulator-name = "vreg_l5a";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a: ldo6 {
+ regulator-name = "vreg_l6a";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a: ldo7 {
+ regulator-name = "vreg_l7a";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8a: ldo8 {
+ regulator-name = "vreg_l8a";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a: ldo9 {
+ regulator-name = "vreg_l9a";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmm8654au-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_s5c: smps5 { /* LPDDR VDD2H */
+ regulator-name = "vreg_s5c";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c: ldo1 { /* LPDDR VDDQ */
+ regulator-name = "vreg_l1c";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <512000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c: ldo2 { /* LPDDR VDD2L */
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c: ldo4 {
+ regulator-name = "vreg_l4c";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c: ldo7 {
+ regulator-name = "vreg_l7c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c: ldo8 { /* LPDDR VDD1 */
+ regulator-name = "vreg_l8c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c: ldo9 { /* QFPROM */
+ regulator-name = "vreg_l9c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&mdss_dp0 {
+ pinctrl-0 = <&dp_hpd>;
+ pinctrl-names = "default";
+};
+
+&mdss_dp0_phy {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l4a>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l5a>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l4a>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs8300/a623_zap.mbn";
+};
+
+&iris {
+ status = "okay";
+};
+
+/* PCIe0 Gen4 x2 */
+&pcie0 {
+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+ <0x100 &pcie_smmu 0x0001 0x1>,
+ <0x200 &pcie_smmu 0x0007 0x1>,
+ <0x208 &pcie_smmu 0x0002 0x1>,
+ <0x210 &pcie_smmu 0x0003 0x1>,
+ <0x218 &pcie_smmu 0x0004 0x1>,
+ <0x300 &pcie_smmu 0x0005 0x1>,
+ <0x400 &pcie_smmu 0x0006 0x1>;
+ num-lanes = <2>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+/* PCIe1 Gen4 x4 */
+&pcie1 {
+ num-lanes = <4>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ firmware-name = "qcom/qcs8300/qupv3fw.elf";
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ firmware-name = "qcom/qcs8300/qupv3fw.elf";
+ status = "okay";
+};
+
+/* There is a HW/FW issue preventing proper REFGEN hardware voting
+ * for the USB2 HS PHY. As a workaround, we force REFGEN to stay
+ * always‑on in software, matching initial bootloader config.
+ */
+&refgen{
+ regulator-always-on;
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8300/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8300/cdsp0.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_gpdsp {
+ firmware-name = "qcom/qcs8300/gpdsp0.mbn";
+
+ status = "okay";
+};
+
+/* Ethernet/SGMII */
+&serdes0 {
+ phy-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&tlmm {
+ dp_hpd: dp-hpd-state {
+ pins = "gpio94";
+ function = "edp0_hot";
+ bias-disable;
+ };
+};
+
+/* USB0 HS + SS */
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l7a>;
+ vdda18-supply = <&vreg_l7c>;
+ vdda33-supply = <&vreg_l9a>;
+
+ status = "okay";
+};
+
+&usb_qmpphy {
+ vdda-phy-supply = <&vreg_l7a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+/* USB1 HS */
+&usb_2_hsphy {
+ vdda-pll-supply = <&vreg_l7a>;
+ vdda18-supply = <&vreg_l7c>;
+ vdda33-supply = <&vreg_l9a>;
+
+ status = "okay";
+};
+
+/* OnSom eMMC */
+&sdhc_1 {
+ vmmc-supply = <&vreg_l8a>;
+ vqmmc-supply = <&vreg_s2s>;
+
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ no-sd;
+ no-sdio;
+ non-removable;
+
+ status = "okay";
+};
--
2.47.3
On 3/9/26 4:24 PM, Srinivas Kandagatla wrote:
> From: Loic Poulain <loic.poulain@oss.qualcomm.com>
>
> The Monaco Monza SoM is a compact computing module that integrates a
> Monaco/QCS8300 System on Chip (SoC), along with essential components
> optimized for IoT applications. It is designed to be mounted on
> carrier boards, enabling the development of complete embedded systems.
>
> The following components are described:
> - Fixed S2S 1.8V rail
> - PMM8654AU RPMh regulators (PMIC A and PMIC C)
> - Display subsystem/phy supplies (DSI, DP)
> - Enable GPU, GPI DMA, IRIS
> - PCIe Gen4 for both controllers and PHY supply hookups
> - QUPv3 firmware declarations
> - REFGEN always-on workaround for USB2 HS PHY
> - Remoteproc firmware names for ADSP, CDSP and GPDSP
> - Ethernet SERDES supplies
> - USB HS/SS PHY regulators
> - On-SoM eMMC
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
> ---
[...]
> +/* PCIe0 Gen4 x2 */
> +&pcie0 {
> + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
> + <0x100 &pcie_smmu 0x0001 0x1>,
> + <0x200 &pcie_smmu 0x0007 0x1>,
> + <0x208 &pcie_smmu 0x0002 0x1>,
> + <0x210 &pcie_smmu 0x0003 0x1>,
> + <0x218 &pcie_smmu 0x0004 0x1>,
> + <0x300 &pcie_smmu 0x0005 0x1>,
> + <0x400 &pcie_smmu 0x0006 0x1>;
> + num-lanes = <2>;
This is already set in monaco.dtsi
[...]
> +/* PCIe1 Gen4 x4 */
> +&pcie1 {
> + num-lanes = <4>;
likewise
[...]
> +&qupv3_id_0 {
> + firmware-name = "qcom/qcs8300/qupv3fw.elf";
> + status = "okay";
Other nodes in this file have a \n before 'status', it'd be neat to have
one everywhere
> +};
> +
> +&qupv3_id_1 {
> + firmware-name = "qcom/qcs8300/qupv3fw.elf";
> + status = "okay";
> +};
> +
> +/* There is a HW/FW issue preventing proper REFGEN hardware voting
> + * for the USB2 HS PHY. As a workaround, we force REFGEN to stay
> + * always‑on in software, matching initial bootloader config.
> + */
> +&refgen{
Please add a space before '{'
[...]
> +/* OnSom eMMC */
> +&sdhc_1 {
This one is out-of-place, alphabetically - please move it up
Konrad
Thanks Konrad,
On 3/10/26 10:39 AM, Konrad Dybcio wrote:
> On 3/9/26 4:24 PM, Srinivas Kandagatla wrote:
>> From: Loic Poulain <loic.poulain@oss.qualcomm.com>
>>
>> The Monaco Monza SoM is a compact computing module that integrates a
>> Monaco/QCS8300 System on Chip (SoC), along with essential components
>> optimized for IoT applications. It is designed to be mounted on
>> carrier boards, enabling the development of complete embedded systems.
>>
>> The following components are described:
>> - Fixed S2S 1.8V rail
>> - PMM8654AU RPMh regulators (PMIC A and PMIC C)
>> - Display subsystem/phy supplies (DSI, DP)
>> - Enable GPU, GPI DMA, IRIS
>> - PCIe Gen4 for both controllers and PHY supply hookups
>> - QUPv3 firmware declarations
>> - REFGEN always-on workaround for USB2 HS PHY
>> - Remoteproc firmware names for ADSP, CDSP and GPDSP
>> - Ethernet SERDES supplies
>> - USB HS/SS PHY regulators
>> - On-SoM eMMC
>>
>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
>> ---
>
> [...]
>
>> +/* PCIe0 Gen4 x2 */
>> +&pcie0 {
>> + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
>> + <0x100 &pcie_smmu 0x0001 0x1>,
>> + <0x200 &pcie_smmu 0x0007 0x1>,
>> + <0x208 &pcie_smmu 0x0002 0x1>,
>> + <0x210 &pcie_smmu 0x0003 0x1>,
>> + <0x218 &pcie_smmu 0x0004 0x1>,
>> + <0x300 &pcie_smmu 0x0005 0x1>,
>> + <0x400 &pcie_smmu 0x0006 0x1>;
>> + num-lanes = <2>;
>
> This is already set in monaco.dtsi
All the comments look fine with me, will fix that in next version.
--srini
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