Hello,

This series add basic support for Microchip "PIC64-HPSC" and "PIC64HX"
(abbreviated "p64h") Ethernet endpoint. Both MPUs contain 4 GEM IP with
support for MII/RGMII/SGMII/USXGMII at rates of 10M to 10G. Only RGMII and
SGMII at a rate of 1G is tested for now. Each GEM IP has 8 priority queues
and the revision register reads 0x220c010e.

One particularity of this instantiation of GEM is that the MDIO controller
within the GEM IP is disconnected from any physical pin and p64h rely on
another standalone MDIO controller. For that reason, I've added a dt
binding rule to forbid phys from being added under the gem DT node. See
patch 2.

The maximum jumbo frame size also seems to be different on p64h (16383)
than what most other platforms use (10240). I've found that I need to
tweak a bit the MTU calculation for this, otherwise the RXBS field of the
DMACFG register overflows. See patch 3 for more details.

p64h also supports other features guarded behind CAPS bit like
MACB_CAPS_QBV but I've omitted those intentionally because I didn't test
these.

Thanks,
Charles

Charles Perry (4):
  dt-bindings: net: cdns,macb: add a compatible for Microchip p64h
  dt-bindings: net: cdns,macb: forbid phy nodes for Microchip p64h
  net: macb: add safeguards for jumbo frame larger than 10240
  net: macb: add support for Microchip p64h ethernet endpoint

 .../devicetree/bindings/net/cdns,macb.yaml       | 12 ++++++++++++
 drivers/net/ethernet/cadence/macb_main.c         | 16 ++++++++++++++--
 2 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.47.3