Hi David
在 2026/03/04 星期三 3:52, David Heidelberg via B4 Relay 写道:
> From: David Heidelberg <david@ixit.cz>
>
> These clocks are used by PCIe lanes, but we're missing from the
> definition.
>
Thanks for catching this.
Since you're already working on the PCIe clock definitions, would you
mind taking the opportunity to also add the missing pcie2x1 pipe clock
to the rk356x-base.dtsi in the same patch? This would keep the fixes
complete and consistent.
> Suggested-by: Charalampos Mitrodimas <charmitro@posteo.net>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 658097ed69714..3bc653f027f1f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 {
> bus-range = <0x10 0x1f>;
> clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
> <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
> - <&cru CLK_PCIE30X1_AUX_NDFT>;
> + <&cru CLK_PCIE30X1_AUX_NDFT>,
> + <&cru CLK_PCIE30X1_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 {
> bus-range = <0x20 0x2f>;
> clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
> <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
> - <&cru CLK_PCIE30X2_AUX_NDFT>;
> + <&cru CLK_PCIE30X2_AUX_NDFT>,
> + <&cru CLK_PCIE30X2_PIPE_DFT>;
> clock-names = "aclk_mst", "aclk_slv",
> - "aclk_dbi", "pclk", "aux";
> + "aclk_dbi", "pclk", "aux",
> + "pipe";
> device_type = "pci";
> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
>