From nobody Thu Apr 9 19:21:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B956435F199; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; cv=none; b=A/QgD7FlGf6QFiIlKbhgBJhqlJLGAzCRz8CDk/k/d401DWTw5BLbfqT+APWrOoMWGKjIT8nZNshJsDyjxBshcXvkdvHMGFmnja/f4UizjmUE1zYB7A+Vhk1JinodLuzYQB4wWp2SUTuT3YHTTn+dKi31GIqajqsyUr9p/+Xdid4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; c=relaxed/simple; bh=oHis0oNWG8f5L9e3rDYPqCCkd9XkQEAtq1esFIHDMUU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ibhjdRVr/J39Ic/7v9cnAeH7RDRKDRXdQtYDh7J821DcHfT/qOL1t+WiH2C28JJ8XsInYU+ZLGoz/GbkHN9l0s2HLKDWKwGCrWVFSnyf8mID907IoAw5J2F+cP9Sd9rcpfIVUGGj2y9QW1LsCBQBq6XhY4HuFLyMcUv9c1P9DAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iJfSUWV/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iJfSUWV/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76775C2BC87; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772567550; bh=oHis0oNWG8f5L9e3rDYPqCCkd9XkQEAtq1esFIHDMUU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iJfSUWV/dv7huAy8kvxJJz4EZlGAgXuzNtuAs9i+2K3ynBZE5LdVQ7+MZnhAxtY5N Y+zdFUFvhULsfAzYhuHRMhiTPnPpc3qyCj38opcCj/RAgYdZhHkhjiNs8UCt8vyUDB 9jaGh020BSVGZ7ExGLMlwhAs/6lJG9ZBKgCg5CxXXlfHdPeSw0EYoz208vtsEQpB/w cEMo02vUbrSaAo0ALQulQZAP4nbySIVpUKZzlYUPNW8a0UQ8PPP7zyNyHaswHMM/Rv H8eyRiEUf55vtTPKOPdevrW81f/yVrflplxoWEHwWsy7APZAYJBY5n0g2W42c1oHCn fvDuEXdnZRx2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58DFDEDEBED; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 20:52:27 +0100 Subject: [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-1-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1684; i=david@ixit.cz; h=from:subject:message-id; bh=kBL8DfIbMEZId/mS9aT/ZMrXznRqWhpDEYin4PccSE4=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBppzv7Wv3xTTAHuxiN/ZqvtT/LDbQ8kHANgL2gf 2gYzFH1ituJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaac7+wAKCRBgAj/E00kg cg18EAC4Hcmjx5yPY78MeXIWdgDG5ds2l3Pxnhjtmy7lALsL4hCfW4aX9rahnv14dF8xPR2D0pP z2m+aVGb7e4fwBBn5TCtS6+TxuZSFbyw9/TTI3te5JcoGtrs8GSAQOl4WtWVRNfOqOVrRqUJk/x feoSjS/zLrcpaBAr5dtw24bdps8H1k+5g/kLV0z9PZd8XHTq1YZwo2Ms5uzYRAVR9qrNEH8TC2J /mJQWinn76+YtotO9QUukpg45y2UzvUtxnA2EoyMQ85SLSiFRYKgmFZDzZZHXj/GIBteQh30MS8 1kXUuGMWpx23ADPgCOESGsEv+VCQ+6plKjSKpMoQhUkpz0zdsH5eDKjw4VX3Ex/24+l42sVDRvc GNgLYWRkJvt6Z2p2Vt+ijJqglH0VZQrkv6MkTrpw7fTo8CgdyRVo0h5zJPPtHoc5I4GB2nUFef/ gvtHFPRERqnXJEhz3P7xoHhgUtZO4H4ALZi+/GbjQb9mAOER2onws7ZtLyveHBR6Ww/jrre7ALG cgMP6BsOTDaYOA2v5gX+gX4JYv/0fVBfbAZT1qLcLEfbFjwh/irNWPlhwQRyri4IaqNKpFjobi2 LwMBnOkWQKQzfUrZ9T0iJEv4zyntNxY5NMPMKg+chORgsV7j51PJIJ/5eswvCyU42dngK5iyaQk FM32cyvEh/DnvrQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg These clocks are used by PCIe lanes, but we're missing from the definition. Suggested-by: Charalampos Mitrodimas Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts= /rockchip/rk3568.dtsi index 658097ed69714..3bc653f027f1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 { bus-range =3D <0x10 0x1f>; clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 { bus-range =3D <0x20 0x2f>; clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , --=20 2.53.0