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[PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support

Luca Ceresoli posted 3 patches 1 month, 1 week ago
[PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support
Posted by Luca Ceresoli 1 month, 1 week ago 
Generation of a test pattern output is a useful tool for panel bringup and
debugging, and very simple to support with this chip.

The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two
for the test pattern to work in dual LVDS mode. While not clearly stated in
the datasheet, this is needed according to the DSI Tuner [0] output. And
some dual-LVDS panels refuse to show any picture without this division by
two.

[0] https://www.ti.com/tool/DSI-TUNER

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
 drivers/gpu/drm/bridge/ti-sn65dsi83.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 17a885244e1e..ddc8b5e1dd15 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -114,6 +114,7 @@
 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH	0x38
 #define REG_VID_CHA_VERTICAL_FRONT_PORCH	0x3a
 #define REG_VID_CHA_TEST_PATTERN		0x3c
+#define  REG_VID_CHA_TEST_PATTERN_EN		BIT(4)
 /* IRQ registers */
 #define REG_IRQ_GLOBAL				0xe0
 #define  REG_IRQ_GLOBAL_IRQ_EN			BIT(0)
@@ -134,6 +135,9 @@
 #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR		BIT(2)
 #define  REG_IRQ_STAT_CHA_PLL_UNLOCK		BIT(0)
 
+static bool sn65dsi83_test_pattern;
+module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
+
 enum sn65dsi83_channel {
 	CHANNEL_A,
 	CHANNEL_B
@@ -645,7 +649,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
 			  REG_LVDS_LANE_CHB_LVDS_TERM : 0));
 	regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
 
-	le16val = cpu_to_le16(mode->hdisplay);
+	/*
+	 * Active line length needs to be halved for test pattern
+	 * generation in dual LVDS output.
+	 */
+	le16val = cpu_to_le16(mode->hdisplay / (sn65dsi83_test_pattern ? 2 : 1));
 	regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
 			  &le16val, 2);
 	le16val = cpu_to_le16(mode->vdisplay);
@@ -668,7 +676,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
 		     (mode->hsync_start - mode->hdisplay) / dual_factor);
 	regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
 		     mode->vsync_start - mode->vdisplay);
-	regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
+	regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN,
+		     sn65dsi83_test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0);
 
 	/* Enable PLL */
 	regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);

-- 
2.53.0
Re: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support
Posted by Luca Ceresoli 1 month, 1 week ago 
Hello,

On Thu Feb 26, 2026 at 5:16 PM CET, Luca Ceresoli wrote:
> Generation of a test pattern output is a useful tool for panel bringup and
> debugging, and very simple to support with this chip.
>
> The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two
> for the test pattern to work in dual LVDS mode. While not clearly stated in
> the datasheet, this is needed according to the DSI Tuner [0] output. And
> some dual-LVDS panels refuse to show any picture without this division by
> two.
>
> [0] https://www.ti.com/tool/DSI-TUNER
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

I just noticed a small glitch in the implementation.

> +static bool sn65dsi83_test_pattern;
> +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
> +
>  enum sn65dsi83_channel {
>  	CHANNEL_A,
>  	CHANNEL_B
> @@ -645,7 +649,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
>  			  REG_LVDS_LANE_CHB_LVDS_TERM : 0));
>  	regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
>
> -	le16val = cpu_to_le16(mode->hdisplay);
> +	/*
> +	 * Active line length needs to be halved for test pattern
> +	 * generation in dual LVDS output.
> +	 */
> +	le16val = cpu_to_le16(mode->hdisplay / (sn65dsi83_test_pattern ? 2 : 1));

In case sn65dsi83_test_pattern is changed from user space after this
cpu_to_le16()...

>  	regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
>  			  &le16val, 2);
>  	le16val = cpu_to_le16(mode->vdisplay);
> @@ -668,7 +676,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
>  		     (mode->hsync_start - mode->hdisplay) / dual_factor);
>  	regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
>  		     mode->vsync_start - mode->vdisplay);
> -	regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
> +	regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN,
> +		     sn65dsi83_test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0);

...but before this regmap_write(), the two registers affected by
sn65dsi83_test_pattern would be written with inconsistent values.

I'm resending with that fixed.

Luca

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support
Posted by Marek Vasut 1 month, 1 week ago 
On 2/26/26 5:16 PM, Luca Ceresoli wrote:
> Generation of a test pattern output is a useful tool for panel bringup and
> debugging, and very simple to support with this chip.
> 
> The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two
> for the test pattern to work in dual LVDS mode. While not clearly stated in
> the datasheet, this is needed according to the DSI Tuner [0] output. And
> some dual-LVDS panels refuse to show any picture without this division by
> two.
> 
> [0] https://www.ti.com/tool/DSI-TUNER
> 
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> ---
>   drivers/gpu/drm/bridge/ti-sn65dsi83.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> index 17a885244e1e..ddc8b5e1dd15 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> @@ -114,6 +114,7 @@
>   #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH	0x38
>   #define REG_VID_CHA_VERTICAL_FRONT_PORCH	0x3a
>   #define REG_VID_CHA_TEST_PATTERN		0x3c
> +#define  REG_VID_CHA_TEST_PATTERN_EN		BIT(4)
>   /* IRQ registers */
>   #define REG_IRQ_GLOBAL				0xe0
>   #define  REG_IRQ_GLOBAL_IRQ_EN			BIT(0)
> @@ -134,6 +135,9 @@
>   #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR		BIT(2)
>   #define  REG_IRQ_STAT_CHA_PLL_UNLOCK		BIT(0)
>   
> +static bool sn65dsi83_test_pattern;
> +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
Can this be enabled/disabled at runtime via sysfs attribute instead ?
Re: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support
Posted by Maxime Ripard 1 month, 1 week ago 
On Fri, Feb 27, 2026 at 11:41:29AM +0100, Marek Vasut wrote:
> On 2/26/26 5:16 PM, Luca Ceresoli wrote:
> > Generation of a test pattern output is a useful tool for panel bringup and
> > debugging, and very simple to support with this chip.
> > 
> > The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two
> > for the test pattern to work in dual LVDS mode. While not clearly stated in
> > the datasheet, this is needed according to the DSI Tuner [0] output. And
> > some dual-LVDS panels refuse to show any picture without this division by
> > two.
> > 
> > [0] https://www.ti.com/tool/DSI-TUNER
> > 
> > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > ---
> >   drivers/gpu/drm/bridge/ti-sn65dsi83.c | 13 +++++++++++--
> >   1 file changed, 11 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > index 17a885244e1e..ddc8b5e1dd15 100644
> > --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> > @@ -114,6 +114,7 @@
> >   #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH	0x38
> >   #define REG_VID_CHA_VERTICAL_FRONT_PORCH	0x3a
> >   #define REG_VID_CHA_TEST_PATTERN		0x3c
> > +#define  REG_VID_CHA_TEST_PATTERN_EN		BIT(4)
> >   /* IRQ registers */
> >   #define REG_IRQ_GLOBAL				0xe0
> >   #define  REG_IRQ_GLOBAL_IRQ_EN			BIT(0)
> > @@ -134,6 +135,9 @@
> >   #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR		BIT(2)
> >   #define  REG_IRQ_STAT_CHA_PLL_UNLOCK		BIT(0)
> > +static bool sn65dsi83_test_pattern;
> > +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
>
> Can this be enabled/disabled at runtime via sysfs attribute instead ?

Then you would have to deal with concurrency with the atomic state
updates, and it would really be better implemented as a connector
property.

In other words, it's probably enough for now :)

Maxime
Re: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support
Posted by Luca Ceresoli 1 month, 1 week ago 
Hello Marek, Maxime,

On Fri Feb 27, 2026 at 11:57 AM CET, Maxime Ripard wrote:
>> > @@ -134,6 +135,9 @@
>> >   #define  REG_IRQ_STAT_CHA_SOT_BIT_ERR		BIT(2)
>> >   #define  REG_IRQ_STAT_CHA_PLL_UNLOCK		BIT(0)
>> > +static bool sn65dsi83_test_pattern;
>> > +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644);
>>
>> Can this be enabled/disabled at runtime via sysfs attribute instead ?
>
> Then you would have to deal with concurrency with the atomic state
> updates, and it would really be better implemented as a connector
> property.
>
> In other words, it's probably enough for now :)

I agree with Maxime, let's keep it simple, especially as it's a debugging
tool and nobody wants to debug a debugging tool. :)

It can be made more complex in the future if there is a real need.

Luca

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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