From nobody Tue Apr 7 18:48:30 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1E5C363C58 for ; Thu, 26 Feb 2026 16:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; cv=none; b=pcusi5/DuooV9aUnEjVXdOa4KL7pTXbK4SB7ClyImwQu1T/w/82AI3xeb+6GzSEKZU8lc4f1vejKR753apN52Ixl89zNhYBwG4Qe0t1ATAFUo/mTOK7seBwOWWbf3HFJfMBYk9fvPNSp0azw4xWIxTx0GysQA0cImkQmBjqMHwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772122679; c=relaxed/simple; bh=j9URmxYZ4o+i61Q3qSSIZFqdDNta1gKMi5z8xWiQi2g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ivA4nyBhx5qOTgmvjC4Ae6PtWCmL9wY0u57se3mQyhZwsRZBiugyhGgrZfZph7ZWpmnX+aVwxqFwRtvbwHnwzDVVZPyBD126gaqEmUM07Oakf9eiTXXxA6cCPhTmxd6SY+Vz3+785+OO5185yAL9lnp0chpWlLt+HSmJZWqExas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=SHZw10H+; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SHZw10H+" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id BFAFC4E41236; Thu, 26 Feb 2026 16:17:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 94A3A5FDE9; Thu, 26 Feb 2026 16:17:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D0A25103693F9; Thu, 26 Feb 2026 17:17:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772122675; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=w5vPufaau/3I2QpJ9e2+Z9v2JqhTHbqrTx3oXaG/ZO4=; b=SHZw10H+CRxh0DMlHtFEARQLTPyEM0rce1xFoOvnREX4YLoCytnQZn7K8oGDwMTn0RWNLX tRLdcrIZzQ49RjSThw8Z3cIBWZ7+LffiQHIpdK578hl5UCFpCyd1eGXhyaeY3aClwuGi90 X4w3RZh1u3fOK4Et881Ya/FA2ZlwXAtYT5gt/gPS9pqzVEzoKGXB/6puAtUM6pc8BtJEzu WroSs6fqNMgHWL5VkqqvU0CBRVWs6pv90Z7dy1D1cVUXs/F+YFOOXPhh/L6L7WaotxZKMm OP94AVuy4REkMxP+fcj5vPEafML0Uw5buzRAc4GikxobSkqYVLQvA484TdCkhA== From: Luca Ceresoli Date: Thu, 26 Feb 2026 17:16:46 +0100 Subject: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-3-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Generation of a test pattern output is a useful tool for panel bringup and debugging, and very simple to support with this chip. The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two for the test pattern to work in dual LVDS mode. While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. And some dual-LVDS panels refuse to show any picture without this division by two. [0] https://www.ti.com/tool/DSI-TUNER Signed-off-by: Luca Ceresoli --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 17a885244e1e..ddc8b5e1dd15 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -114,6 +114,7 @@ #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a #define REG_VID_CHA_TEST_PATTERN 0x3c +#define REG_VID_CHA_TEST_PATTERN_EN BIT(4) /* IRQ registers */ #define REG_IRQ_GLOBAL 0xe0 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) @@ -134,6 +135,9 @@ #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) =20 +static bool sn65dsi83_test_pattern; +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); + enum sn65dsi83_channel { CHANNEL_A, CHANNEL_B @@ -645,7 +649,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bri= dge *bridge, REG_LVDS_LANE_CHB_LVDS_TERM : 0)); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); =20 - le16val =3D cpu_to_le16(mode->hdisplay); + /* + * Active line length needs to be halved for test pattern + * generation in dual LVDS output. + */ + le16val =3D cpu_to_le16(mode->hdisplay / (sn65dsi83_test_pattern ? 2 : 1)= ); regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, &le16val, 2); le16val =3D cpu_to_le16(mode->vdisplay); @@ -668,7 +676,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, (mode->hsync_start - mode->hdisplay) / dual_factor); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, mode->vsync_start - mode->vdisplay); - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, + sn65dsi83_test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); =20 /* Enable PLL */ regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); --=20 2.53.0