The CPU power management issue in the CTI driver was first observed in
series [1]; this series resolves that issue. It fixes bugs and removes
CPU PM operations from the CoreSight CTI driver, the goal is to use the
CoreSight core layer as the central place for CPU power management.
Removing CPU PM from CTI driver can avoid conflicts with the core layer.
This series can be divided into:
Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS
lock.
Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code,
and refactor register access in sysfs knob.
This series is based on coresight-next branch and has been validated on
Juno r2 platforms, pass normal sysfs and perf test, as well as CPU PM
stress testing.
[1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-0-ea49e91124ec@arm.com/
Signed-off-by: Leo Yan <leo.yan@arm.com>
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Changes in v2:
- Rebased on coresight-next branch (v7.1).
- Kept read/write cache value in sysfs knob (Mike).
- Link to v1: https://lore.kernel.org/r/20260209-arm_coresight_cti_refactor_v1-v1-0-db71ab4d200b@arm.com
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Leo Yan (8):
coresight: cti: Make spinlock usage consistent
coresight: cti: Fix register reads
coresight: cti: Access ASICCTL only when implemented
coresight: cti: Remove CPU power management code
coresight: cti: Rename cti_active() to cti_is_active()
coresight: cti: Remove hw_powered flag
coresight: cti: Remove hw_enabled flag
coresight: cti: Properly handle negative offsets in cti_reg32_{show|store}()
drivers/hwtracing/coresight/coresight-cti-core.c | 278 ++++------------------
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 171 ++++++-------
drivers/hwtracing/coresight/coresight-cti.h | 13 +-
3 files changed, 137 insertions(+), 325 deletions(-)
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base-commit: eef33a7cce239783d0422526a4d786289a936f1b
change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716
Best regards,
--
Leo Yan <leo.yan@arm.com>