From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 490C63A1CE1 for ; Thu, 26 Feb 2026 09:24:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097844; cv=none; b=K/LjxIntJW1kvYZG6pyrTMGLftnPIcCe738PKZ77p+SRXaJRM7hSvQy7Gcc3YsIbHFsGrPoFKaWwQDTW/h87GOuMPKHTUwV2tWOWho5T9UJt+Df9u8taIm8Y/mjz92W3X5FmcYIo4tHDIXxSNzyjZO6XUVtirVZqlqBHC+F5A5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097844; c=relaxed/simple; bh=pMfExa9UsfodncwklBjNdHqOpkjX5bE7fYev2ubLSyQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ElmzaX3vw6zMKXDXM0JSAtIH3rSsmE72aCpX6h8YK96KyF8lzqKTZwD/JBWliNtOA2yn8S8HmqLKHHbWK+L5ftABG5hqrPl6XxHqlQiOpij9iIvDSwLVr+Qp7iDK1Y3qucMKvUGHWEPilcVl+2oRNxunR0KHxcUJGXrRLJ69zx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 73DE7153B; Thu, 26 Feb 2026 01:23:55 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BF8B63F62B; Thu, 26 Feb 2026 01:23:59 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:49 +0000 Subject: [PATCH v2 1/8] coresight: cti: Make spinlock usage consistent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-1-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=18093; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=pMfExa9UsfodncwklBjNdHqOpkjX5bE7fYev2ubLSyQ=; b=445vKHEYfCWjkHTyXtp6m1m4hWND8wIC+v/BB/8CqfOqJWmtCVNw+/BiOm7Rg34Fe/clA1wex +9bBWbN/jbLCXJBoB8lfQMiX6KWSgXvIRUpsPfCuu7qE7b6NM8IadHB X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The spinlock is acquired sometimes with IRQs disabled and sometimes without. This leads to inconsistent semantics: the lock can be either HARDIRQ-safe or HARDIRQ-unsafe, which may trigger lockdep complaints. Make spinlock usage consistent by acquiring it with disabling IRQs. It is possible for sysfs knobs to acquire the spinlock for accessing a CTI device, while at the same time a perf session sends an IPI to enable the same CTI device. In this case, the spinlock must be IRQ-safe, which is why all lock acquisitions are changed to disable IRQs. Use guard() and scoped_guard() for spinlock to tidy up the code. Fixes: 984f37efa385 ("coresight: cti: Write regsiters directly in cti_enabl= e_hw()") Tested-by: James Clark Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 74 ++++------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 145 ++++++++++++------= ---- 2 files changed, 103 insertions(+), 116 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index fddc8f31b91dccba1506aae8c2fd5f348240b98b..e3c98d89c987c10faafa02d1dbd= 721cfd4187edb 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -81,10 +81,9 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) static int cti_enable_hw(struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; - unsigned long flags; - int rc =3D 0; + int rc; =20 - raw_spin_lock_irqsave(&drvdata->spinlock, flags); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* no need to do anything if enabled or unpowered*/ if (config->hw_enabled || !config->hw_powered) @@ -93,22 +92,15 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) /* claim the device */ rc =3D coresight_claim_device(drvdata->csdev); if (rc) - goto cti_err_not_enabled; + return rc; =20 cti_write_all_hw_regs(drvdata); =20 config->hw_enabled =3D true; - drvdata->config.enable_req_count++; - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - return rc; =20 cti_state_unchanged: drvdata->config.enable_req_count++; - - /* cannot enable due to error */ -cti_err_not_enabled: - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - return rc; + return 0; } =20 /* re-enable CTI on CPU when using CPU hotplug */ @@ -116,25 +108,21 @@ static void cti_cpuhp_enable_hw(struct cti_drvdata *d= rvdata) { struct cti_config *config =3D &drvdata->config; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + config->hw_powered =3D true; =20 /* no need to do anything if no enable request */ if (!drvdata->config.enable_req_count) - goto cti_hp_not_enabled; + return; =20 /* try to claim the device */ if (coresight_claim_device(drvdata->csdev)) - goto cti_hp_not_enabled; + return; =20 cti_write_all_hw_regs(drvdata); config->hw_enabled =3D true; - raw_spin_unlock(&drvdata->spinlock); return; - - /* did not re-enable due to no claim / no request */ -cti_hp_not_enabled: - raw_spin_unlock(&drvdata->spinlock); } =20 /* disable hardware */ @@ -142,23 +130,20 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; - int ret =3D 0; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* don't allow negative refcounts, return an error */ - if (!drvdata->config.enable_req_count) { - ret =3D -EINVAL; - goto cti_not_disabled; - } + if (!drvdata->config.enable_req_count) + return -EINVAL; =20 /* check refcount - disable on 0 */ if (--drvdata->config.enable_req_count > 0) - goto cti_not_disabled; + return 0; =20 /* no need to do anything if disabled or cpu unpowered */ if (!config->hw_enabled || !config->hw_powered) - goto cti_not_disabled; + return 0; =20 CS_UNLOCK(drvdata->base); =20 @@ -168,13 +153,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) =20 coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); - raw_spin_unlock(&drvdata->spinlock); - return ret; - - /* not disabled this call */ -cti_not_disabled: - raw_spin_unlock(&drvdata->spinlock); - return ret; + return 0; } =20 void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) @@ -189,11 +168,11 @@ void cti_write_intack(struct device *dev, u32 ackval) struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + /* write if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, CTIINTACK, ackval); - raw_spin_unlock(&drvdata->spinlock); } =20 /* @@ -360,7 +339,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : CTIOUTEN(trigger_idx)); =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* read - modify write - the trigger / channel enable value */ reg_value =3D direction =3D=3D CTI_TRIG_IN ? config->ctiinen[trigger_idx]= : @@ -379,7 +358,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, /* write through if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, reg_offset, reg_value); - raw_spin_unlock(&drvdata->spinlock); + return 0; } =20 @@ -397,7 +376,8 @@ int cti_channel_gate_op(struct device *dev, enum cti_ch= an_gate_op op, =20 chan_bitmask =3D BIT(channel_idx); =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + reg_value =3D config->ctigate; switch (op) { case CTI_GATE_CHAN_ENABLE: @@ -417,7 +397,7 @@ int cti_channel_gate_op(struct device *dev, enum cti_ch= an_gate_op op, if (cti_active(config)) cti_write_single_reg(drvdata, CTIGATE, reg_value); } - raw_spin_unlock(&drvdata->spinlock); + return err; } =20 @@ -436,7 +416,8 @@ int cti_channel_setop(struct device *dev, enum cti_chan= _set_op op, =20 chan_bitmask =3D BIT(channel_idx); =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + reg_value =3D config->ctiappset; switch (op) { case CTI_CHAN_SET: @@ -464,7 +445,6 @@ int cti_channel_setop(struct device *dev, enum cti_chan= _set_op op, =20 if ((err =3D=3D 0) && cti_active(config)) cti_write_single_reg(drvdata, reg_offset, reg_value); - raw_spin_unlock(&drvdata->spinlock); =20 return err; } @@ -667,7 +647,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb,= unsigned long cmd, if (WARN_ON_ONCE(drvdata->ctidev.cpu !=3D cpu)) return NOTIFY_BAD; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 switch (cmd) { case CPU_PM_ENTER: @@ -707,7 +687,6 @@ static int cti_cpu_pm_notify(struct notifier_block *nb,= unsigned long cmd, } =20 cti_notify_exit: - raw_spin_unlock(&drvdata->spinlock); return notify_res; } =20 @@ -734,11 +713,12 @@ static int cti_dying_cpu(unsigned int cpu) if (!drvdata) return 0; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + drvdata->config.hw_powered =3D false; if (drvdata->config.hw_enabled) coresight_disclaim_device(drvdata->csdev); - raw_spin_unlock(&drvdata->spinlock); + return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 572b80ee96fbf18ec8cf9abc30d109a676dfbc5d..455d08bcccd49a3f1eac8abd824= 6806ef73a9ab6 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -84,11 +84,11 @@ static ssize_t enable_show(struct device *dev, bool enabled, powered; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - enable_req =3D drvdata->config.enable_req_count; - powered =3D drvdata->config.hw_powered; - enabled =3D drvdata->config.hw_enabled; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + enable_req =3D drvdata->config.enable_req_count; + powered =3D drvdata->config.hw_powered; + enabled =3D drvdata->config.hw_enabled; + } =20 if (powered) return sprintf(buf, "%d\n", enabled); @@ -134,9 +134,8 @@ static ssize_t powered_show(struct device *dev, bool powered; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - powered =3D drvdata->config.hw_powered; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) + powered =3D drvdata->config.hw_powered; =20 return sprintf(buf, "%d\n", powered); } @@ -181,10 +180,12 @@ static ssize_t coresight_cti_reg_show(struct device *= dev, u32 val =3D 0; =20 pm_runtime_get_sync(dev->parent); - raw_spin_lock(&drvdata->spinlock); - if (drvdata->config.hw_powered) - val =3D readl_relaxed(drvdata->base + cti_attr->off); - raw_spin_unlock(&drvdata->spinlock); + + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + if (drvdata->config.hw_powered) + val =3D readl_relaxed(drvdata->base + cti_attr->off); + } + pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); } @@ -202,10 +203,12 @@ static __maybe_unused ssize_t coresight_cti_reg_store= (struct device *dev, return -EINVAL; =20 pm_runtime_get_sync(dev->parent); - raw_spin_lock(&drvdata->spinlock); - if (drvdata->config.hw_powered) - cti_write_single_reg(drvdata, cti_attr->off, val); - raw_spin_unlock(&drvdata->spinlock); + + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + if (drvdata->config.hw_powered) + cti_write_single_reg(drvdata, cti_attr->off, val); + } + pm_runtime_put_sync(dev->parent); return size; } @@ -264,17 +267,18 @@ static ssize_t cti_reg32_show(struct device *dev, cha= r *buf, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; =20 - raw_spin_lock(&drvdata->spinlock); - if ((reg_offset >=3D 0) && cti_active(config)) { - CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + reg_offset); - if (pcached_val) - *pcached_val =3D val; - CS_LOCK(drvdata->base); - } else if (pcached_val) { - val =3D *pcached_val; + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + if ((reg_offset >=3D 0) && cti_active(config)) { + CS_UNLOCK(drvdata->base); + val =3D readl_relaxed(drvdata->base + reg_offset); + if (pcached_val) + *pcached_val =3D val; + CS_LOCK(drvdata->base); + } else if (pcached_val) { + val =3D *pcached_val; + } } - raw_spin_unlock(&drvdata->spinlock); + return sprintf(buf, "%#x\n", val); } =20 @@ -293,15 +297,16 @@ static ssize_t cti_reg32_store(struct device *dev, co= nst char *buf, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); - /* local store */ - if (pcached_val) - *pcached_val =3D (u32)val; + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + /* local store */ + if (pcached_val) + *pcached_val =3D (u32)val; + + /* write through if offset and enabled */ + if ((reg_offset >=3D 0) && cti_active(config)) + cti_write_single_reg(drvdata, reg_offset, val); + } =20 - /* write through if offset and enabled */ - if ((reg_offset >=3D 0) && cti_active(config)) - cti_write_single_reg(drvdata, reg_offset, val); - raw_spin_unlock(&drvdata->spinlock); return size; } =20 @@ -349,9 +354,9 @@ static ssize_t inout_sel_store(struct device *dev, if (val > (CTIINOUTEN_MAX - 1)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + drvdata->config.ctiinout_sel =3D val; - raw_spin_unlock(&drvdata->spinlock); return size; } static DEVICE_ATTR_RW(inout_sel); @@ -364,10 +369,11 @@ static ssize_t inen_show(struct device *dev, int index; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - index =3D drvdata->config.ctiinout_sel; - val =3D drvdata->config.ctiinen[index]; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + index =3D drvdata->config.ctiinout_sel; + val =3D drvdata->config.ctiinen[index]; + } + return sprintf(buf, "%#lx\n", val); } =20 @@ -383,14 +389,15 @@ static ssize_t inen_store(struct device *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + index =3D config->ctiinout_sel; config->ctiinen[index] =3D val; =20 /* write through if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, CTIINEN(index), val); - raw_spin_unlock(&drvdata->spinlock); + return size; } static DEVICE_ATTR_RW(inen); @@ -403,10 +410,11 @@ static ssize_t outen_show(struct device *dev, int index; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - index =3D drvdata->config.ctiinout_sel; - val =3D drvdata->config.ctiouten[index]; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + index =3D drvdata->config.ctiinout_sel; + val =3D drvdata->config.ctiouten[index]; + } + return sprintf(buf, "%#lx\n", val); } =20 @@ -422,14 +430,15 @@ static ssize_t outen_store(struct device *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + index =3D config->ctiinout_sel; config->ctiouten[index] =3D val; =20 /* write through if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, CTIOUTEN(index), val); - raw_spin_unlock(&drvdata->spinlock); + return size; } static DEVICE_ATTR_RW(outen); @@ -463,7 +472,7 @@ static ssize_t appclear_store(struct device *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* a 1'b1 in appclr clears down the same bit in appset*/ config->ctiappset &=3D ~val; @@ -471,7 +480,7 @@ static ssize_t appclear_store(struct device *dev, /* write through if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, CTIAPPCLEAR, val); - raw_spin_unlock(&drvdata->spinlock); + return size; } static DEVICE_ATTR_WO(appclear); @@ -487,12 +496,12 @@ static ssize_t apppulse_store(struct device *dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* write through if enabled */ if (cti_active(config)) cti_write_single_reg(drvdata, CTIAPPPULSE, val); - raw_spin_unlock(&drvdata->spinlock); + return size; } static DEVICE_ATTR_WO(apppulse); @@ -681,9 +690,9 @@ static ssize_t trig_filter_enable_show(struct device *d= ev, u32 val; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - val =3D drvdata->config.trig_filter_enable; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) + val =3D drvdata->config.trig_filter_enable; + return sprintf(buf, "%d\n", val); } =20 @@ -697,9 +706,9 @@ static ssize_t trig_filter_enable_store(struct device *= dev, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + drvdata->config.trig_filter_enable =3D !!val; - raw_spin_unlock(&drvdata->spinlock); return size; } static DEVICE_ATTR_RW(trig_filter_enable); @@ -728,7 +737,7 @@ static ssize_t chan_xtrigs_reset_store(struct device *d= ev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* clear the CTI trigger / channel programming registers */ for (i =3D 0; i < config->nr_trig_max; i++) { @@ -747,7 +756,6 @@ static ssize_t chan_xtrigs_reset_store(struct device *d= ev, if (cti_active(config)) cti_write_all_hw_regs(drvdata); =20 - raw_spin_unlock(&drvdata->spinlock); return size; } static DEVICE_ATTR_WO(chan_xtrigs_reset); @@ -768,9 +776,9 @@ static ssize_t chan_xtrigs_sel_store(struct device *dev, if (val > (drvdata->config.nr_ctm_channels - 1)) return -EINVAL; =20 - raw_spin_lock(&drvdata->spinlock); + guard(raw_spinlock_irqsave)(&drvdata->spinlock); + drvdata->config.xtrig_rchan_sel =3D val; - raw_spin_unlock(&drvdata->spinlock); return size; } =20 @@ -781,9 +789,8 @@ static ssize_t chan_xtrigs_sel_show(struct device *dev, unsigned long val; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - raw_spin_lock(&drvdata->spinlock); - val =3D drvdata->config.xtrig_rchan_sel; - raw_spin_unlock(&drvdata->spinlock); + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) + val =3D drvdata->config.xtrig_rchan_sel; =20 return sprintf(buf, "%ld\n", val); } @@ -838,12 +845,12 @@ static ssize_t print_chan_list(struct device *dev, unsigned long inuse_bits =3D 0, chan_mask; =20 /* scan regs to get bitmap of channels in use. */ - raw_spin_lock(&drvdata->spinlock); - for (i =3D 0; i < config->nr_trig_max; i++) { - inuse_bits |=3D config->ctiinen[i]; - inuse_bits |=3D config->ctiouten[i]; + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + for (i =3D 0; i < config->nr_trig_max; i++) { + inuse_bits |=3D config->ctiinen[i]; + inuse_bits |=3D config->ctiouten[i]; + } } - raw_spin_unlock(&drvdata->spinlock); =20 /* inverse bits if printing free channels */ if (!inuse) --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 79B3F3A1A27 for ; Thu, 26 Feb 2026 09:24:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097845; cv=none; b=E24z7zUKd8WMMsvrz4s94JFbAIvkBATxGGbBHaA/j/KXsypafa0v6jgtgJub23dH0a5/vZ/I0UhX8nXl9XbGUMKa/9WSNLrnowcMAe4dPaHX5cZMbiwoEoV2yViqMHPdno6BRJy8Rv6IXvosePHkmffw75sq+chzovUnnujwZh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097845; c=relaxed/simple; bh=2bQ69Z5ouesbi+b2Bz2ZVyq089jUDRdtmH85bguxG+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KaOzeGzMXtyS6t3F/sqgnUhHYN6xYlLh6BxP+Bnz5srsJ+Tzja7fUgSPUhgdpVoj0i3cVo1Wbtk77vY6md2GxBA4KbNiF0YjTEw1xe8d1BEdopujVleH1tQzH0dqfq5okma1iq7rN21ZLLVnnyNP926gRCojaK9qyuptK5XRbDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96C4B15A1; Thu, 26 Feb 2026 01:23:57 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0CEB13F62B; Thu, 26 Feb 2026 01:24:01 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:50 +0000 Subject: [PATCH v2 2/8] coresight: cti: Fix register reads Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-2-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=3389; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=2bQ69Z5ouesbi+b2Bz2ZVyq089jUDRdtmH85bguxG+k=; b=k+kMKN3OT97s4KtA2QvxnO51Usv4KLzWaUnRqYONXAfCuTXwavXsxV/+NilWag42GKw3vgHmF 2fmwV5/nbr/AhaQTsFZWg8/qH8tP+Qr0kkUKO2lHtJKzoeExpNjfUAL X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Introduce cti_read_single_reg() as an interface for reading registers with unlocking the CS lock. Consolidate register read in sysfs interfaces using this new helper. Fixes: b5213376c240 ("coresight: cti: Add sysfs access to program function = registers") Fixes: 1a556ca6cc24 ("coresight: cti: Add sysfs coresight mgmt register acc= ess") Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 11 +++++++++++ drivers/hwtracing/coresight/coresight-cti-sysfs.c | 6 ++---- drivers/hwtracing/coresight/coresight-cti.h | 1 + 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index e3c98d89c987c10faafa02d1dbd721cfd4187edb..6a53c3ceebf41645e599017e076= d12b8b158b10f 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -156,6 +156,17 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) return 0; } =20 +u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) +{ + int val; + + CS_UNLOCK(drvdata->base); + val =3D readl_relaxed(drvdata->base + offset); + CS_LOCK(drvdata->base); + + return val; +} + void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) { CS_UNLOCK(drvdata->base); diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 455d08bcccd49a3f1eac8abd8246806ef73a9ab6..9a997b2f090472761e9734fffc5= 34663df8b06c6 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -183,7 +183,7 @@ static ssize_t coresight_cti_reg_show(struct device *de= v, =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { if (drvdata->config.hw_powered) - val =3D readl_relaxed(drvdata->base + cti_attr->off); + val =3D cti_read_single_reg(drvdata, cti_attr->off); } =20 pm_runtime_put_sync(dev->parent); @@ -269,11 +269,9 @@ static ssize_t cti_reg32_show(struct device *dev, char= *buf, =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { if ((reg_offset >=3D 0) && cti_active(config)) { - CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + reg_offset); + val =3D cti_read_single_reg(drvdata, reg_offset); if (pcached_val) *pcached_val =3D val; - CS_LOCK(drvdata->base); } else if (pcached_val) { val =3D *pcached_val; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index daff9e32a6daca90f4d5f4726f163fdd9106191c..45735526fe55b0e4746ba856443= f0fcc807d82bb 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -220,6 +220,7 @@ int cti_disable(struct coresight_device *csdev, struct = coresight_path *path); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue); +u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 84DCB3A7843 for ; Thu, 26 Feb 2026 09:24:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097847; cv=none; b=tFm4xUMDHDDnYzRyK95Zj908z+0kXdb9v2FqX/I03712rWIAiG6bOJ8d0PBXCBj6tsjUbRgQ+f1OxdXDLxsK7fWXiXYaGz02YrpvsNB400mDtrOLSRAuJBpLrMlDMR1gBynKCRGAQOjecT9IA75vKgNaW99l83SUZK+EONm35so= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097847; c=relaxed/simple; bh=rGuLCxcdB51oZkB3MVY5dJcQ0/iYvhTpnGJEDPotNFE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K24bA+WRXSorlWtD/LlOlNEFP07EcrjXa6la/x0tHFbcTI2zmUoMVUTf8R9M06ktQUigfUP6jVidF37U0fNhuhiweB60XH1XyIfRrONy1rZVkGnKwONt1qMWT7JEwzAwctRwkoStUY0bnzbRUSRqM01iYW4KvYETu/ep7XxXVFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7CEC1516; Thu, 26 Feb 2026 01:23:59 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2FEE23F62B; Thu, 26 Feb 2026 01:24:04 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:51 +0000 Subject: [PATCH v2 3/8] coresight: cti: Access ASICCTL only when implemented Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-3-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=3849; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=rGuLCxcdB51oZkB3MVY5dJcQ0/iYvhTpnGJEDPotNFE=; b=NopYtP6OyEKzNL1XEVEYATIrioauyFYSNuqAHV7n7bnBsVZQhuyY96j1ay/2BGNSAG9FPV1af 8mnblQn5DZQAPfTcgG1lGeAHH18G38G26u7Eg6Fb7UR21Ue8b/e7hgN X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= According to the Arm ARM (DDI 0487 L.b), ASICCTL is implemented only when CTIDEVID.EXTMUXNUM is non-zero. Based on CTIDEVID.EXTMUXNUM, add a flag 'asicctl_impl' to indicate whether the register is implemented, and access ASICCTL conditionally based on the flag. Allow the sysfs node to be visible only when the register is implemented. Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 5 ++++- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 13 +++++++++++++ drivers/hwtracing/coresight/coresight-cti.h | 2 ++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 6a53c3ceebf41645e599017e076d12b8b158b10f..726970d852dee3b962e5147311d= fadd0b741cfe0 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -68,7 +68,8 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* other regs */ writel_relaxed(config->ctigate, drvdata->base + CTIGATE); - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); + if (config->asicctl_impl) + writel_relaxed(config->asicctl, drvdata->base + ASICCTL); writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); =20 /* re-enable CTI */ @@ -221,6 +222,8 @@ static void cti_set_default_config(struct device *dev, config->trig_filter_enable =3D true; config->ctigate =3D GENMASK(config->nr_ctm_channels - 1, 0); config->enable_req_count =3D 0; + + config->asicctl_impl =3D !!FIELD_GET(GENMASK(4, 0), devid); } =20 /* diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 9a997b2f090472761e9734fffc534663df8b06c6..c15a580f6e90f57b1376e0b883a= 27700966feb1a 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -537,6 +537,18 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { NULL, }; =20 +static umode_t coresight_cti_regs_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + if (attr =3D=3D &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) + return 0; + + return attr->mode; +} + /* CTI channel x-trigger programming */ static int cti_trig_op_parse(struct device *dev, enum cti_chan_op op, @@ -1174,6 +1186,7 @@ static const struct attribute_group coresight_cti_mgm= t_group =3D { =20 static const struct attribute_group coresight_cti_regs_group =3D { .attrs =3D coresight_cti_regs_attrs, + .is_visible =3D coresight_cti_regs_is_visible, .name =3D "regs", }; =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 45735526fe55b0e4746ba856443f0fcc807d82bb..a4b3968d8d3d19a20604fb09db1= 4cf41962f5a79 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -119,6 +119,7 @@ struct cti_device { * @nr_trig_max: Max number of trigger signals implemented on device. * (max of trig_in or trig_out) - from ID register. * @nr_ctm_channels: number of available CTM channels - from ID register. + * @asicctl_impl: true if asicctl is implemented. * @enable_req_count: CTI is enabled alongside >=3D1 associated devices. * @hw_enabled: true if hw is currently enabled. * @hw_powered: true if associated cpu powered on, or no cpu. @@ -140,6 +141,7 @@ struct cti_config { /* hardware description */ int nr_ctm_channels; int nr_trig_max; + bool asicctl_impl; =20 /* cti enable control */ int enable_req_count; --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC11F3A0B31 for ; Thu, 26 Feb 2026 09:24:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097850; cv=none; b=pKdBN8fu30qoNEIse4MW7FrcqtBcy2ZC6jrZE2NyqlT2r3uBqSSuTTlQy5j9RuzrNTJM4LatBB4gec+RhN0/6b8gguHgJ/mhYNCUIQEX+ayOoeXVC02Ayn9NDROIK1SMKMHsCNgIXz1997OAfmorTS3uG0Yvo27+9KEO9PusJ60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097850; c=relaxed/simple; bh=mdbLwyTm6Utwn6BUDv5t9NwB7q+u7LCs3OuT4P2ZvRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YpQNUcw4U7re83xz2j+Sd5Dw0IqadkMno69ntimHaexnJgVFYy9thUVghLn+iNJKE0tnYH6GwdhObecqdpXAKKKPxIxpyPmZmxNmtCu/mDY1mzTfo/puumP0+EYlXWAxh0r1VRalAttxOnAiKi/mQF5A6dAA/w1EdVlWPyVsvGY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB6F4153B; Thu, 26 Feb 2026 01:24:01 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 541C03F62B; Thu, 26 Feb 2026 01:24:06 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:52 +0000 Subject: [PATCH v2 4/8] coresight: cti: Remove CPU power management code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-4-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=7475; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=mdbLwyTm6Utwn6BUDv5t9NwB7q+u7LCs3OuT4P2ZvRA=; b=nlM+vxhL9vvs7OOBgAjuPhOHGzP19a0i3NykDPUlOltCrLeqeumj6soRz+56HC/Swqm5Eslz5 LeZIbWvV/8kB/dIpQSPDf+CYgTgR6rm3RI6d7pFW83l9VMS/BZeFZ3w X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= According Arm ARM, the CTI ASICCTL register: "It is IMPLEMENTATION DEFINED whether ASICCTL is implemented in the Core power domain or in the Debug power domain." This is the only CTI register that may reside in the core power domain. However, it has been confirmed that Arm designed CTIs place ASICCTL in the debug power domain. Furthermore, ASICCTL is implemented only when CTIDEVID.EXTMUXNUM is non-zero, which is a rare case for CPU CTIs. For these reasons, it is safe to conclude that all CTI registers are not located in the CPU power domain. Therefore, the CTI driver does not need CPU power management. This commit removes the CPU power management from CTI driver. Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 186 +------------------= ---- 1 file changed, 3 insertions(+), 183 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 726970d852dee3b962e5147311dfadd0b741cfe0..3aa081f28a18dc4987feeb57244= aa384e80702ac 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -42,12 +42,6 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) =20 -/* power management handling */ -static int nr_cti_cpu; - -/* quick lookup list for CPU bound CTIs when power handling */ -static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; - /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -104,28 +98,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) return 0; } =20 -/* re-enable CTI on CPU when using CPU hotplug */ -static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) -{ - struct cti_config *config =3D &drvdata->config; - - guard(raw_spinlock_irqsave)(&drvdata->spinlock); - - config->hw_powered =3D true; - - /* no need to do anything if no enable request */ - if (!drvdata->config.enable_req_count) - return; - - /* try to claim the device */ - if (coresight_claim_device(drvdata->csdev)) - return; - - cti_write_all_hw_regs(drvdata); - config->hw_enabled =3D true; - return; -} - /* disable hardware */ static int cti_disable_hw(struct cti_drvdata *drvdata) { @@ -643,146 +615,6 @@ static void cti_remove_conn_xrefs(struct cti_drvdata = *drvdata) } } =20 -/** cti PM callbacks **/ -static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, - void *v) -{ - struct cti_drvdata *drvdata; - struct coresight_device *csdev; - unsigned int cpu =3D smp_processor_id(); - int notify_res =3D NOTIFY_OK; - - if (!cti_cpu_drvdata[cpu]) - return NOTIFY_OK; - - drvdata =3D cti_cpu_drvdata[cpu]; - csdev =3D drvdata->csdev; - - if (WARN_ON_ONCE(drvdata->ctidev.cpu !=3D cpu)) - return NOTIFY_BAD; - - guard(raw_spinlock_irqsave)(&drvdata->spinlock); - - switch (cmd) { - case CPU_PM_ENTER: - /* CTI regs all static - we have a copy & nothing to save */ - drvdata->config.hw_powered =3D false; - if (drvdata->config.hw_enabled) - coresight_disclaim_device(csdev); - break; - - case CPU_PM_ENTER_FAILED: - drvdata->config.hw_powered =3D true; - if (drvdata->config.hw_enabled) { - if (coresight_claim_device(csdev)) - drvdata->config.hw_enabled =3D false; - } - break; - - case CPU_PM_EXIT: - /* write hardware registers to re-enable. */ - drvdata->config.hw_powered =3D true; - drvdata->config.hw_enabled =3D false; - - /* check enable reference count to enable HW */ - if (drvdata->config.enable_req_count) { - /* check we can claim the device as we re-power */ - if (coresight_claim_device(csdev)) - goto cti_notify_exit; - - drvdata->config.hw_enabled =3D true; - cti_write_all_hw_regs(drvdata); - } - break; - - default: - notify_res =3D NOTIFY_DONE; - break; - } - -cti_notify_exit: - return notify_res; -} - -static struct notifier_block cti_cpu_pm_nb =3D { - .notifier_call =3D cti_cpu_pm_notify, -}; - -/* CPU HP handlers */ -static int cti_starting_cpu(unsigned int cpu) -{ - struct cti_drvdata *drvdata =3D cti_cpu_drvdata[cpu]; - - if (!drvdata) - return 0; - - cti_cpuhp_enable_hw(drvdata); - return 0; -} - -static int cti_dying_cpu(unsigned int cpu) -{ - struct cti_drvdata *drvdata =3D cti_cpu_drvdata[cpu]; - - if (!drvdata) - return 0; - - guard(raw_spinlock_irqsave)(&drvdata->spinlock); - - drvdata->config.hw_powered =3D false; - if (drvdata->config.hw_enabled) - coresight_disclaim_device(drvdata->csdev); - - return 0; -} - -static int cti_pm_setup(struct cti_drvdata *drvdata) -{ - int ret; - - if (drvdata->ctidev.cpu =3D=3D -1) - return 0; - - if (nr_cti_cpu) - goto done; - - cpus_read_lock(); - ret =3D cpuhp_setup_state_nocalls_cpuslocked( - CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, - "arm/coresight_cti:starting", - cti_starting_cpu, cti_dying_cpu); - if (ret) { - cpus_read_unlock(); - return ret; - } - - ret =3D cpu_pm_register_notifier(&cti_cpu_pm_nb); - cpus_read_unlock(); - if (ret) { - cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_CTI_STARTING); - return ret; - } - -done: - nr_cti_cpu++; - cti_cpu_drvdata[drvdata->ctidev.cpu] =3D drvdata; - - return 0; -} - -/* release PM registrations */ -static void cti_pm_release(struct cti_drvdata *drvdata) -{ - if (drvdata->ctidev.cpu =3D=3D -1) - return; - - cti_cpu_drvdata[drvdata->ctidev.cpu] =3D NULL; - if (--nr_cti_cpu =3D=3D 0) { - cpu_pm_unregister_notifier(&cti_cpu_pm_nb); - cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_CTI_STARTING); - } -} - /** cti ect operations **/ int cti_enable(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path) @@ -815,7 +647,6 @@ static void cti_remove(struct amba_device *adev) =20 mutex_lock(&ect_mutex); cti_remove_conn_xrefs(drvdata); - cti_pm_release(drvdata); =20 /* remove from the list */ list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) { @@ -889,17 +720,12 @@ static int cti_probe(struct amba_device *adev, const = struct amba_id *id) if (!cti_desc.name) return -ENOMEM; =20 - /* setup CPU power management handling for CPU bound CTI devices. */ - ret =3D cti_pm_setup(drvdata); - if (ret) - return ret; - /* create dynamic attributes for connections */ ret =3D cti_create_cons_sysfs(dev, drvdata); if (ret) { dev_err(dev, "%s: create dynamic sysfs entries failed\n", cti_desc.name); - goto pm_release; + return ret; } =20 /* set up coresight component description */ @@ -912,10 +738,8 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) =20 coresight_clear_self_claim_tag(&cti_desc.access); drvdata->csdev =3D coresight_register(&cti_desc); - if (IS_ERR(drvdata->csdev)) { - ret =3D PTR_ERR(drvdata->csdev); - goto pm_release; - } + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); =20 /* add to list of CTI devices */ mutex_lock(&ect_mutex); @@ -928,10 +752,6 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CTI initialized\n"); return 0; - -pm_release: - cti_pm_release(drvdata); - return ret; } =20 static struct amba_cs_uci_id uci_id_cti[] =3D { --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CD7312E1C6B for ; Thu, 26 Feb 2026 09:24:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097852; cv=none; b=E+bIGQ1j7XaPDi+4hdFXeJ+khuVcN0B6d6kWXXInjV39Ot76I8B7SJtILwny1/y3zzt3UFkmhn02m4z+1oKMug6y4ZFsgTj4kCcoa/RHy857S9r1/hHLSrgRkjJa2+Po0RgTZiQJ2Xhokae/nWIeJqPbAXtYZZdyKN1DwwL7TOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097852; c=relaxed/simple; bh=LKf0+zIOAvFxqwOjIyBxQWi1rV+ios78mbayLWnkfbE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EJuOcLgJQSspsjAWijHqPNpYPPHdPFgiAW+Xg6jDjkekcOjsWFdfTGbXg90tAkyGnMOjAX/dqiycHpAGJ2RP0JXqryVj2rXzzeNC1kPidkUCmd7fqw3cU4EzfnmSTWSo97nUjGXKNUgcluc/mhHvbCqREbeLOjaCWPcq0/Nh0r8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A2C91516; Thu, 26 Feb 2026 01:24:04 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 76F243F62B; Thu, 26 Feb 2026 01:24:08 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:53 +0000 Subject: [PATCH v2 5/8] coresight: cti: Rename cti_active() to cti_is_active() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-5-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=4970; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=LKf0+zIOAvFxqwOjIyBxQWi1rV+ios78mbayLWnkfbE=; b=7jHHz9JREV2rs03Tnvu6TEp76RCmoMPIYDGMmji9pat3YQh+teFeOagTiTVewSKoChSoazFcC GH8f/+RulT2AXBwjj/j79QWu41Ld+79a6ma67JwHrAgkQjQlM8YPapv X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Rename cti_active() to cti_is_active() to clarify that it checks whether the CTI device is active. Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 8 ++++---- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 14 +++++++------- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 3aa081f28a18dc4987feeb57244aa384e80702ac..28f995263433c8727a7fdeff94f= be0a4286767e8 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -155,7 +155,7 @@ void cti_write_intack(struct device *dev, u32 ackval) guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* write if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIINTACK, ackval); } =20 @@ -342,7 +342,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, config->ctiouten[trigger_idx] =3D reg_value; =20 /* write through if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, reg_offset, reg_value); =20 return 0; @@ -380,7 +380,7 @@ int cti_channel_gate_op(struct device *dev, enum cti_ch= an_gate_op op, } if (err =3D=3D 0) { config->ctigate =3D reg_value; - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIGATE, reg_value); } =20 @@ -429,7 +429,7 @@ int cti_channel_setop(struct device *dev, enum cti_chan= _set_op op, break; } =20 - if ((err =3D=3D 0) && cti_active(config)) + if ((err =3D=3D 0) && cti_is_active(config)) cti_write_single_reg(drvdata, reg_offset, reg_value); =20 return err; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index c15a580f6e90f57b1376e0b883a27700966feb1a..a22cc9a2bee24eb6115e7adb618= 80cc86d03e12e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -268,7 +268,7 @@ static ssize_t cti_reg32_show(struct device *dev, char = *buf, struct cti_config *config =3D &drvdata->config; =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { - if ((reg_offset >=3D 0) && cti_active(config)) { + if ((reg_offset >=3D 0) && cti_is_active(config)) { val =3D cti_read_single_reg(drvdata, reg_offset); if (pcached_val) *pcached_val =3D val; @@ -301,7 +301,7 @@ static ssize_t cti_reg32_store(struct device *dev, cons= t char *buf, *pcached_val =3D (u32)val; =20 /* write through if offset and enabled */ - if ((reg_offset >=3D 0) && cti_active(config)) + if ((reg_offset >=3D 0) && cti_is_active(config)) cti_write_single_reg(drvdata, reg_offset, val); } =20 @@ -393,7 +393,7 @@ static ssize_t inen_store(struct device *dev, config->ctiinen[index] =3D val; =20 /* write through if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIINEN(index), val); =20 return size; @@ -434,7 +434,7 @@ static ssize_t outen_store(struct device *dev, config->ctiouten[index] =3D val; =20 /* write through if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIOUTEN(index), val); =20 return size; @@ -476,7 +476,7 @@ static ssize_t appclear_store(struct device *dev, config->ctiappset &=3D ~val; =20 /* write through if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIAPPCLEAR, val); =20 return size; @@ -497,7 +497,7 @@ static ssize_t apppulse_store(struct device *dev, guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* write through if enabled */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, CTIAPPPULSE, val); =20 return size; @@ -763,7 +763,7 @@ static ssize_t chan_xtrigs_reset_store(struct device *d= ev, config->xtrig_rchan_sel =3D 0; =20 /* if enabled then write through */ - if (cti_active(config)) + if (cti_is_active(config)) cti_write_all_hw_regs(drvdata); =20 return size; diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index a4b3968d8d3d19a20604fb09db14cf41962f5a79..2edc0d01812c93fe5a817da366a= 2862b8490c0a3 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -236,7 +236,7 @@ coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); =20 /* cti powered and enabled */ -static inline bool cti_active(struct cti_config *cfg) +static inline bool cti_is_active(struct cti_config *cfg) { return cfg->hw_powered && cfg->hw_enabled; } --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EB867399021 for ; Thu, 26 Feb 2026 09:24:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097854; cv=none; b=Urc+sWvwbNGP9YwUpk3id+p+Yh55R56ari1ivtZ3e6GLcIMym2CTccL49brKmJzYfkOGflFTmXmHt7eDRJ40ObIV3cicY2gBLqYmrnTSpqhP6hrRkLJxgcLd0ZBWy6287mqO7shKJH13W5T+O+Nwc4Hw+dlLOy8///mtUq/IF2M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097854; c=relaxed/simple; bh=78HBWw3rZu//Oc2CWmqhk0gfqqlUfI4gCU5MKgBJLA4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=THIcNwog4aErVvoHLMwpiSUet2x1AuUeX9Bq10uWzAZ58P+PtE7cyBgitQ/4IFlshOtmgsYlwIJf4uuqooovAhNk6rZAa8xAEPjJAkhSGajfFN+MdE3PfmMJVslJINOnvZXuCjb7wWaKLu5SKEgEuVoiyugKiK46b68oHvXmwpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D057153B; Thu, 26 Feb 2026 01:24:06 -0800 (PST) Received: from e132581.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9AD123F62B; Thu, 26 Feb 2026 01:24:10 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:54 +0000 Subject: [PATCH v2 6/8] coresight: cti: Remove hw_powered flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-6-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=5776; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=78HBWw3rZu//Oc2CWmqhk0gfqqlUfI4gCU5MKgBJLA4=; b=H+KfhLtRJtC5PI/IxROZVUJYG4amXN9yb96yJqVfRm43W+sjwq38uDbykBPnVtw2XW/rWIfMd 4RqOZ5XLJ+lDlWIwItdTaY9ilz5arWB0fmBWLbqnXR9XQC3Gpzyjpee X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Since the CPU PM code has been removed from the CTI driver and the device is enabled via runtime PM, pm_runtime_active() can be used to check whether the device is powered. As a result, the hw_powered flag is redundant, remove it. Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 11 ++++----- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 29 ++++++-------------= ---- drivers/hwtracing/coresight/coresight-cti.h | 6 ++--- 3 files changed, 13 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 28f995263433c8727a7fdeff94fbe0a4286767e8..5ac36f0776181559a87b3ee37d6= c9076882576b5 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -80,8 +80,8 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 - /* no need to do anything if enabled or unpowered*/ - if (config->hw_enabled || !config->hw_powered) + /* no need to do anything if enabled */ + if (config->hw_enabled) goto cti_state_unchanged; =20 /* claim the device */ @@ -114,8 +114,8 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) if (--drvdata->config.enable_req_count > 0) return 0; =20 - /* no need to do anything if disabled or cpu unpowered */ - if (!config->hw_enabled || !config->hw_powered) + /* no need to do anything if disabled */ + if (!config->hw_enabled) return 0; =20 CS_UNLOCK(drvdata->base); @@ -702,9 +702,6 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) return PTR_ERR(pdata); } =20 - /* default to powered - could change on PM notifications */ - drvdata->config.hw_powered =3D true; - /* * Set up device name - will depend if cpu bound or otherwise. * diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index a22cc9a2bee24eb6115e7adb61880cc86d03e12e..9ab586a5c9a4fd2a64c542aaaaa= 625e2299edd62 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -81,19 +81,12 @@ static ssize_t enable_show(struct device *dev, char *buf) { int enable_req; - bool enabled, powered; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) enable_req =3D drvdata->config.enable_req_count; - powered =3D drvdata->config.hw_powered; - enabled =3D drvdata->config.hw_enabled; - } =20 - if (powered) - return sprintf(buf, "%d\n", enabled); - else - return sprintf(buf, "%d\n", !!enable_req); + return sprintf(buf, "%d\n", !!enable_req); } =20 static ssize_t enable_store(struct device *dev, @@ -131,11 +124,7 @@ static ssize_t powered_show(struct device *dev, struct device_attribute *attr, char *buf) { - bool powered; - struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); - - scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - powered =3D drvdata->config.hw_powered; + bool powered =3D pm_runtime_active(dev->parent); =20 return sprintf(buf, "%d\n", powered); } @@ -181,10 +170,8 @@ static ssize_t coresight_cti_reg_show(struct device *d= ev, =20 pm_runtime_get_sync(dev->parent); =20 - scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { - if (drvdata->config.hw_powered) - val =3D cti_read_single_reg(drvdata, cti_attr->off); - } + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) + val =3D cti_read_single_reg(drvdata, cti_attr->off); =20 pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); @@ -204,10 +191,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, =20 pm_runtime_get_sync(dev->parent); =20 - scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { - if (drvdata->config.hw_powered) - cti_write_single_reg(drvdata, cti_attr->off, val); - } + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) + cti_write_single_reg(drvdata, cti_attr->off, val); =20 pm_runtime_put_sync(dev->parent); return size; diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 2edc0d01812c93fe5a817da366a2862b8490c0a3..8754cb5def7918f032353438444= 67af8410b75a8 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -122,7 +122,6 @@ struct cti_device { * @asicctl_impl: true if asicctl is implemented. * @enable_req_count: CTI is enabled alongside >=3D1 associated devices. * @hw_enabled: true if hw is currently enabled. - * @hw_powered: true if associated cpu powered on, or no cpu. * @trig_in_use: bitfield of in triggers registered as in use. * @trig_out_use: bitfield of out triggers registered as in use. * @trig_out_filter: bitfield of out triggers that are blocked if filter @@ -146,7 +145,6 @@ struct cti_config { /* cti enable control */ int enable_req_count; bool hw_enabled; - bool hw_powered; =20 /* registered triggers and filtering */ u32 trig_in_use; @@ -235,10 +233,10 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); =20 -/* cti powered and enabled */ +/* Check if a cti device is enabled */ static inline bool cti_is_active(struct cti_config *cfg) { - return cfg->hw_powered && cfg->hw_enabled; + return cfg->hw_enabled; } =20 #endif /* _CORESIGHT_CORESIGHT_CTI_H */ --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1537C3A1D1F for ; Thu, 26 Feb 2026 09:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097856; cv=none; b=gF/ciVN/LSI5LBvm0NgikAPs5H2UmzPYsK+2U2LveGirbXxJgCkE08bj9chcy8XzbUeGc1EaN2b4LF01gfHuycjSxQmEf7DlTjvUpKrnfDc7fppnt9+ENnKrAjWle1qDplOAYveW3Ir8YMZv4lzfqRJJuU9qxVGdVHDTv1PaYbI= ARC-Message-Signature: i=1; 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Thu, 26 Feb 2026 01:24:12 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:55 +0000 Subject: [PATCH v2 7/8] coresight: cti: Remove hw_enabled flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-7-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=4151; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=g2L3i1CezfA6Jf1Jke+6/YKaXLSWcNpqDPO+Nh3fXjw=; b=xvlMausvbKO7aFJ/w3JHJfQomLjTikxfuO3Vyt4MebonledDtqJ7hAzsENFJ4+LJHKZ/+9nbr +UuSOaeDK4gDwqblAMgK9iGzswvwhDh1gNcD6Kvr3yaBgfk6ausbqsc X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= The enable_req_count field already tracks whether the CTI device is enabled. A non-zero value indicates that the device is active, the hw_enabled flag is redundant if so. Remove hw_enabled and update cti_is_active() to check enable_req_count. Replace open-coded enable_req_count checks with cti_is_active(). Reviewed-by: Mike Leach Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 11 ++--------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-cti.h | 4 +--- 3 files changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 5ac36f0776181559a87b3ee37d6c9076882576b5..2f4c9362709a90b12a1aeb50169= 05b7d4474b912 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -81,7 +81,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* no need to do anything if enabled */ - if (config->hw_enabled) + if (cti_is_active(config)) goto cti_state_unchanged; =20 /* claim the device */ @@ -91,8 +91,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) =20 cti_write_all_hw_regs(drvdata); =20 - config->hw_enabled =3D true; - cti_state_unchanged: drvdata->config.enable_req_count++; return 0; @@ -107,22 +105,17 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 /* don't allow negative refcounts, return an error */ - if (!drvdata->config.enable_req_count) + if (!cti_is_active(config)) return -EINVAL; =20 /* check refcount - disable on 0 */ if (--drvdata->config.enable_req_count > 0) return 0; =20 - /* no need to do anything if disabled */ - if (!config->hw_enabled) - return 0; - CS_UNLOCK(drvdata->base); =20 /* disable CTI */ writel_relaxed(0, drvdata->base + CTICONTROL); - config->hw_enabled =3D false; =20 coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 9ab586a5c9a4fd2a64c542aaaaa625e2299edd62..9ef44956ebdc7781717d773fa01= 4165989df2048 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -84,7 +84,7 @@ static ssize_t enable_show(struct device *dev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - enable_req =3D drvdata->config.enable_req_count; + enable_req =3D cti_is_active(&drvdata->config); =20 return sprintf(buf, "%d\n", !!enable_req); } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 8754cb5def7918f03235343844467af8410b75a8..c5f9e79fabc608f5a95e7e4d8b0= cbe1c853d584a 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -121,7 +121,6 @@ struct cti_device { * @nr_ctm_channels: number of available CTM channels - from ID register. * @asicctl_impl: true if asicctl is implemented. * @enable_req_count: CTI is enabled alongside >=3D1 associated devices. - * @hw_enabled: true if hw is currently enabled. * @trig_in_use: bitfield of in triggers registered as in use. * @trig_out_use: bitfield of out triggers registered as in use. * @trig_out_filter: bitfield of out triggers that are blocked if filter @@ -144,7 +143,6 @@ struct cti_config { =20 /* cti enable control */ int enable_req_count; - bool hw_enabled; =20 /* registered triggers and filtering */ u32 trig_in_use; @@ -236,7 +234,7 @@ const char *cti_plat_get_node_name(struct fwnode_handle= *fwnode); /* Check if a cti device is enabled */ static inline bool cti_is_active(struct cti_config *cfg) { - return cfg->hw_enabled; + return !!cfg->enable_req_count; } =20 #endif /* _CORESIGHT_CORESIGHT_CTI_H */ --=20 2.34.1 From nobody Thu Apr 2 11:22:45 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4F7223A0EBB for ; Thu, 26 Feb 2026 09:24:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772097858; cv=none; b=j70oLJAz1pst1Ybq4KnbPTMQ/VWo9tzMC5Mkj1Ycj0CtukzCa7CwlWhVnpdoNoWGOw3qNrJXe/up9Jwfzu6QMijr8rc0xm0hWNnhUmaC3/fZLrKTSBuRmm4xxGHH15fEuy9PoLzxFSXqwYZ6CMnt/hRRCPCkywDDMWfowcnFjh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 26 Feb 2026 01:24:14 -0800 (PST) From: Leo Yan Date: Thu, 26 Feb 2026 09:23:56 +0000 Subject: [PATCH v2 8/8] coresight: cti: Properly handle negative offsets in cti_reg32_{show|store}() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260226-arm_coresight_cti_refactor_v1-v2-8-b30fada3cfec@arm.com> References: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> In-Reply-To: <20260226-arm_coresight_cti_refactor_v1-v2-0-b30fada3cfec@arm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Tingwei Zhang , Yingchao Deng , Jie Gan , Yabin Cui Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772097837; l=1566; i=leo.yan@arm.com; s=20250604; h=from:subject:message-id; bh=ye21p2Z8xpYMwCHdRE3woYwpjNxaruoyhn86mQr557I=; b=EKYiu4kRhBuqL+Uo0b2d48MeSRDH0H4DurSO6lej+Cw/AkGUN4wa+c0nsR4rjs/34IaolNNxN nfRLdjrlhf8B4c4FuZ+hfvm4sHJgqhlQ/iVdZQ7IH74dW6BNj+EXvSX X-Developer-Key: i=leo.yan@arm.com; a=ed25519; pk=k4BaDbvkCXzBFA7Nw184KHGP5thju8lKqJYIrOWxDhI= Return an error when the offset is negative. Signed-off-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 9ef44956ebdc7781717d773fa014165989df2048..4c0a60840efb9ecc47850c1eb5a= 7abb41b49c5cc 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -252,8 +252,11 @@ static ssize_t cti_reg32_show(struct device *dev, char= *buf, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; =20 + if (reg_offset < 0) + return -EINVAL; + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { - if ((reg_offset >=3D 0) && cti_is_active(config)) { + if (cti_is_active(config)) { val =3D cti_read_single_reg(drvdata, reg_offset); if (pcached_val) *pcached_val =3D val; @@ -280,13 +283,16 @@ static ssize_t cti_reg32_store(struct device *dev, co= nst char *buf, if (kstrtoul(buf, 0, &val)) return -EINVAL; =20 + if (reg_offset < 0) + return -EINVAL; + scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { /* local store */ if (pcached_val) *pcached_val =3D (u32)val; =20 /* write through if offset and enabled */ - if ((reg_offset >=3D 0) && cti_is_active(config)) + if (cti_is_active(config)) cti_write_single_reg(drvdata, reg_offset, val); } =20 --=20 2.34.1