drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add GPIO set_config to allow setting GPIO specific functionalities.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 863e779dda02..641ae1adfd4a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
rzg2l_gpio_direction_input(chip, offset);
}
+static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ switch (pinconf_to_config_param(config)) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ case PIN_CONFIG_SLEW_RATE:
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ case PIN_CONFIG_POWER_SOURCE:
+ return pinctrl_gpio_set_config(chip, offset, config);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static const char * const rzg2l_gpio_names[] = {
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
@@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
chip->direction_output = rzg2l_gpio_direction_output;
chip->get = rzg2l_gpio_get;
chip->set = rzg2l_gpio_set;
+ chip->set_config = rzg2l_gpio_set_config;
chip->label = name;
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
--
2.43.0Hi Claudiu,
On Wed, 18 Feb 2026 at 16:19, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add GPIO set_config to allow setting GPIO specific functionalities.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
> rzg2l_gpio_direction_input(chip, offset);
> }
>
> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
> + unsigned long config)
> +{
> + switch (pinconf_to_config_param(config)) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> + case PIN_CONFIG_DRIVE_PUSH_PULL:
> + case PIN_CONFIG_SLEW_RATE:
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> + case PIN_CONFIG_POWER_SOURCE:
Shouldn't you handle all types that are supported by
rzg2l_pinctrl_pinconf_[gs]et()?
The following are missing:
PIN_CONFIG_INPUT_ENABLE
PIN_CONFIG_OUTPUT_ENABLE
PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS
PIN_CONFIG_INPUT_SCHMITT_ENABLE
RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
> + return pinctrl_gpio_set_config(chip, offset, config);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static const char * const rzg2l_gpio_names[] = {
> "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
> "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi, Geert,
On 3/13/26 15:15, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Wed, 18 Feb 2026 at 16:19, Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Add GPIO set_config to allow setting GPIO specific functionalities.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
>> rzg2l_gpio_direction_input(chip, offset);
>> }
>>
>> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
>> + unsigned long config)
>> +{
>> + switch (pinconf_to_config_param(config)) {
>> + case PIN_CONFIG_BIAS_DISABLE:
>> + case PIN_CONFIG_BIAS_PULL_UP:
>> + case PIN_CONFIG_BIAS_PULL_DOWN:
>> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
>> + case PIN_CONFIG_DRIVE_PUSH_PULL:
>> + case PIN_CONFIG_SLEW_RATE:
>> + case PIN_CONFIG_DRIVE_STRENGTH:
>> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
>> + case PIN_CONFIG_POWER_SOURCE:
>
> Shouldn't you handle all types that are supported by
> rzg2l_pinctrl_pinconf_[gs]et()?
>
> The following are missing:
> PIN_CONFIG_INPUT_ENABLE
> PIN_CONFIG_OUTPUT_ENABLE
> PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS
> PIN_CONFIG_INPUT_SCHMITT_ENABLE
> RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
I'll add these as well.
Thank you for your review,
Claudiu
Hi Claudiu,
On Mon, 16 Mar 2026 at 11:19, claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
> On 3/13/26 15:15, Geert Uytterhoeven wrote:
> > On Wed, 18 Feb 2026 at 16:19, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Add GPIO set_config to allow setting GPIO specific functionalities.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
> >> rzg2l_gpio_direction_input(chip, offset);
> >> }
> >>
> >> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
> >> + unsigned long config)
> >> +{
> >> + switch (pinconf_to_config_param(config)) {
> >> + case PIN_CONFIG_BIAS_DISABLE:
> >> + case PIN_CONFIG_BIAS_PULL_UP:
> >> + case PIN_CONFIG_BIAS_PULL_DOWN:
> >> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> >> + case PIN_CONFIG_DRIVE_PUSH_PULL:
> >> + case PIN_CONFIG_SLEW_RATE:
> >> + case PIN_CONFIG_DRIVE_STRENGTH:
> >> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> >> + case PIN_CONFIG_POWER_SOURCE:
> >
> > Shouldn't you handle all types that are supported by
> > rzg2l_pinctrl_pinconf_[gs]et()?
> >
> > The following are missing:
> > PIN_CONFIG_INPUT_ENABLE
> > PIN_CONFIG_OUTPUT_ENABLE
> > PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS
> > PIN_CONFIG_INPUT_SCHMITT_ENABLE
> > RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
>
> I'll add these as well.
Apparently you can't just add RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
to the switch statement, as gcc requires all case statements to use values
that are actually defined in the enum:
drivers/pinctrl/renesas/pinctrl-rzg2l.c:2072:9: error: case value
‘128’ not in enumerated type ‘enum pin_config_param’ [-Werror=switch]
As the documentation states this range is meant for custom
configurations:
* @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
* you need to pass in custom configurations to the pin controller, use
* PIN_CONFIG_END+1 as the base offset.
* @PIN_CONFIG_MAX: this is the maximum configuration value that can be
* presented using the packed format.
I fixed that by replacing the enum by u8 in the conversion macros:
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -173,9 +173,9 @@ enum pin_config_param {
* upper 24 bits.
*/
-static inline enum pin_config_param
pinconf_to_config_param(unsigned long config)
+static inline u8 pinconf_to_config_param(unsigned long config)
{
- return (enum pin_config_param) (config & 0xffUL);
+ return config & 0xffUL;
}
static inline u32 pinconf_to_config_argument(unsigned long config)
@@ -183,8 +183,7 @@ static inline u32
pinconf_to_config_argument(unsigned long config)
return (u32) ((config >> 8) & 0xffffffUL);
}
-static inline unsigned long pinconf_to_config_packed(enum
pin_config_param param,
- u32 argument)
+static inline unsigned long pinconf_to_config_packed(u8 param,
u32 argument)
{
return PIN_CONF_PACKED(param, argument);
}
Probably a few more should be updated, too?
> >> @@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> >> chip->direction_output = rzg2l_gpio_direction_output;
> >> chip->get = rzg2l_gpio_get;
> >> chip->set = rzg2l_gpio_set;
> >> + chip->set_config = rzg2l_gpio_set_config;
> >> chip->label = name;
> >> chip->parent = pctrl->dev;
> >> chip->owner = THIS_MODULE;
This change breaks pin control and GPIO on RZ/Five:
-pinctrl-rzg2l 11030000.pinctrl: pinctrl-rzg2l support registered
+gpio gpiochip0: (11030000.pinctrl): setup of own GPIO can0_stb failed
+requesting hog GPIO can0_stb (chip 11030000.pinctrl, offset 18) failed, -95
+gpiochip_add_data_with_key: GPIOs 512..743 (11030000.pinctrl)
failed to register, -95
+pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add
GPIO controller
+pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add GPIO chip
+pinctrl-rzg2l 11030000.pinctrl: probe with driver pinctrl-rzg2l
failed with error -95
For the can0_stb hog, rzg2l_gpio_set_config() is called with offset 18 and
config 0x115 (PIN_CONFIG_PERSIST_STATE = 1).
Just adding PIN_CONFIG_PERSIST_STATE to the switch doesn't help,
as pinctrl_gpio_set_config() also returns -EOPNOTSUPP.
Ignoring PIN_CONFIG_PERSIST_STATE helps a bit, but the next call
uses config 0x8, and pinctrl_gpio_set_config() now returns -EINVAL,
but the pin controller now gets registered?...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi, Geert,
On 3/24/26 19:28, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Mon, 16 Mar 2026 at 11:19, claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>> On 3/13/26 15:15, Geert Uytterhoeven wrote:
>>> On Wed, 18 Feb 2026 at 16:19, Claudiu <claudiu.beznea@tuxon.dev> wrote:
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> Add GPIO set_config to allow setting GPIO specific functionalities.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>
>>> Thanks for your patch!
>>>
>>>> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>>>> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
>>>> rzg2l_gpio_direction_input(chip, offset);
>>>> }
>>>>
>>>> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
>>>> + unsigned long config)
>>>> +{
>>>> + switch (pinconf_to_config_param(config)) {
>>>> + case PIN_CONFIG_BIAS_DISABLE:
>>>> + case PIN_CONFIG_BIAS_PULL_UP:
>>>> + case PIN_CONFIG_BIAS_PULL_DOWN:
>>>> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
>>>> + case PIN_CONFIG_DRIVE_PUSH_PULL:
>>>> + case PIN_CONFIG_SLEW_RATE:
>>>> + case PIN_CONFIG_DRIVE_STRENGTH:
>>>> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
>>>> + case PIN_CONFIG_POWER_SOURCE:
>>>
>>> Shouldn't you handle all types that are supported by
>>> rzg2l_pinctrl_pinconf_[gs]et()?
>>>
>>> The following are missing:
>>> PIN_CONFIG_INPUT_ENABLE
>>> PIN_CONFIG_OUTPUT_ENABLE
>>> PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS
>>> PIN_CONFIG_INPUT_SCHMITT_ENABLE
>>> RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
>>
>> I'll add these as well.
>
> Apparently you can't just add RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE
> to the switch statement, as gcc requires all case statements to use values
> that are actually defined in the enum:
>
> drivers/pinctrl/renesas/pinctrl-rzg2l.c:2072:9: error: case value
> ‘128’ not in enumerated type ‘enum pin_config_param’ [-Werror=switch]
>
> As the documentation states this range is meant for custom
> configurations:
>
> * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
> * you need to pass in custom configurations to the pin controller, use
> * PIN_CONFIG_END+1 as the base offset.
> * @PIN_CONFIG_MAX: this is the maximum configuration value that can be
> * presented using the packed format.
>
> I fixed that by replacing the enum by u8 in the conversion macros:
>
> --- a/include/linux/pinctrl/pinconf-generic.h
> +++ b/include/linux/pinctrl/pinconf-generic.h
> @@ -173,9 +173,9 @@ enum pin_config_param {
> * upper 24 bits.
> */
>
> -static inline enum pin_config_param
> pinconf_to_config_param(unsigned long config)
> +static inline u8 pinconf_to_config_param(unsigned long config)
> {
> - return (enum pin_config_param) (config & 0xffUL);
> + return config & 0xffUL;
> }
>
> static inline u32 pinconf_to_config_argument(unsigned long config)
> @@ -183,8 +183,7 @@ static inline u32
> pinconf_to_config_argument(unsigned long config)
> return (u32) ((config >> 8) & 0xffffffUL);
> }
>
> -static inline unsigned long pinconf_to_config_packed(enum
> pin_config_param param,
> - u32 argument)
> +static inline unsigned long pinconf_to_config_packed(u8 param,
> u32 argument)
> {
> return PIN_CONF_PACKED(param, argument);
> }
>
> Probably a few more should be updated, too?
>
>>>> @@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
>>>> chip->direction_output = rzg2l_gpio_direction_output;
>>>> chip->get = rzg2l_gpio_get;
>>>> chip->set = rzg2l_gpio_set;
>>>> + chip->set_config = rzg2l_gpio_set_config;
>>>> chip->label = name;
>>>> chip->parent = pctrl->dev;
>>>> chip->owner = THIS_MODULE;
>
> This change breaks pin control and GPIO on RZ/Five:
>
> -pinctrl-rzg2l 11030000.pinctrl: pinctrl-rzg2l support registered
> +gpio gpiochip0: (11030000.pinctrl): setup of own GPIO can0_stb failed
> +requesting hog GPIO can0_stb (chip 11030000.pinctrl, offset 18) failed, -95
> +gpiochip_add_data_with_key: GPIOs 512..743 (11030000.pinctrl)
> failed to register, -95
> +pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add
> GPIO controller
> +pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add GPIO chip
> +pinctrl-rzg2l 11030000.pinctrl: probe with driver pinctrl-rzg2l
> failed with error -95
Thank you for looking to this. I haven't experimented this with my RZ/G2L desk
board but looking on other RZ/G2L board that I have access to (not on my desk) I
can see similar errors even on RZ/G2L. I'll look into it.
Thank you,
Claudiu
>
> For the can0_stb hog, rzg2l_gpio_set_config() is called with offset 18 and
> config 0x115 (PIN_CONFIG_PERSIST_STATE = 1).
>
> Just adding PIN_CONFIG_PERSIST_STATE to the switch doesn't help,
> as pinctrl_gpio_set_config() also returns -EOPNOTSUPP.
> Ignoring PIN_CONFIG_PERSIST_STATE helps a bit, but the next call
> uses config 0x8, and pinctrl_gpio_set_config() now returns -EINVAL,
> but the pin controller now gets registered?...
>
> Gr{oetje,eeting}s,
>
> Geert
>
On Tue, 24 Mar 2026 at 18:28, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, 16 Mar 2026 at 11:19, claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
> > On 3/13/26 15:15, Geert Uytterhoeven wrote:
> > > On Wed, 18 Feb 2026 at 16:19, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > >>
> > >> Add GPIO set_config to allow setting GPIO specific functionalities.
> > >>
> > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> This change breaks pin control and GPIO on RZ/Five:
>
> -pinctrl-rzg2l 11030000.pinctrl: pinctrl-rzg2l support registered
> +gpio gpiochip0: (11030000.pinctrl): setup of own GPIO can0_stb failed
> +requesting hog GPIO can0_stb (chip 11030000.pinctrl, offset 18) failed, -95
> +gpiochip_add_data_with_key: GPIOs 512..743 (11030000.pinctrl)
> failed to register, -95
> +pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add
> GPIO controller
> +pinctrl-rzg2l 11030000.pinctrl: error -EOPNOTSUPP: failed to add GPIO chip
> +pinctrl-rzg2l 11030000.pinctrl: probe with driver pinctrl-rzg2l
> failed with error -95
And apart from also breaking mmc0 (probably due to gpio hogs not
working), it causes spurious interrupts on the Ethernet PHY:
Microchip KSZ9131 Gigabit PHY 11c30000.ethernet-ffffffff:07:
attached PHY driver (mii_bus:phy_addr=11c30000.ethernet-ffffffff:07,
irq=38)
[...]
+irq 38: nobody cared (try booting with the "irqpoll" option)
+CPU: 0 UID: 0 PID: 63 Comm: irq/38-11c30000 Not tainted
7.0.0-rc5-rzfive-07159-g46ccdb62e0e4 #488 PREEMPT
+Hardware name: Renesas SMARC EVK based on r9a07g043f01 (DT)
+Call Trace:
+[<ffffffff80010c84>] dump_backtrace+0x1c/0x24
+[<ffffffff80001226>] show_stack+0x2a/0x34
+[<ffffffff8000c338>] dump_stack_lvl+0x32/0x4a
+[<ffffffff8000c364>] dump_stack+0x14/0x1c
+[<ffffffff80002588>] __report_bad_irq+0x30/0xc0
+[<ffffffff80060034>] note_interrupt+0x12c/0x1d2
+[<ffffffff8005dbf0>] handle_irq_event_percpu+0x30/0x3e
+[<ffffffff8005dc36>] handle_irq_event+0x38/0x66
+[<ffffffff80060fac>] handle_fasteoi_irq+0xa0/0xf6
+[<ffffffff8005d574>] handle_irq_desc+0x2c/0x3a
+[<ffffffff8005d5d4>] generic_handle_domain_irq+0x12/0x1a
+[<ffffffff8039c61e>] plic_handle_irq+0x8a/0xb4
+[<ffffffff8005d574>] handle_irq_desc+0x2c/0x3a
+[<ffffffff8005d5d4>] generic_handle_domain_irq+0x12/0x1a
+[<ffffffff80399dfe>] riscv_intc_irq+0x24/0x5c
+[<ffffffff806bb730>] handle_riscv_irq+0x34/0x4c
+[<ffffffff806c2bf4>] call_on_irq_stack+0x1c/0x28
+handlers:
+[<00000000be751d25>] irq_default_primary_handler threaded
[<000000000ed82730>] phy_interrupt
+Disabling IRQ #38
NFS root does work.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, Feb 18, 2026 at 4:19 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add GPIO set_config to allow setting GPIO specific functionalities. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Excellent use of the generic pinctrl backend facility. Reviewed-by: Linus Walleij <linusw@kernel.org> Yours, Linus Walleij
On Wed, Feb 18, 2026 at 3:19 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
>
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add GPIO set_config to allow setting GPIO specific functionalities.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 863e779dda02..641ae1adfd4a 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
> rzg2l_gpio_direction_input(chip, offset);
> }
>
> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
> + unsigned long config)
> +{
> + switch (pinconf_to_config_param(config)) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> + case PIN_CONFIG_DRIVE_PUSH_PULL:
> + case PIN_CONFIG_SLEW_RATE:
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> + case PIN_CONFIG_POWER_SOURCE:
> + return pinctrl_gpio_set_config(chip, offset, config);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static const char * const rzg2l_gpio_names[] = {
> "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
> "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
> @@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> chip->direction_output = rzg2l_gpio_direction_output;
> chip->get = rzg2l_gpio_get;
> chip->set = rzg2l_gpio_set;
> + chip->set_config = rzg2l_gpio_set_config;
> chip->label = name;
> chip->parent = pctrl->dev;
> chip->owner = THIS_MODULE;
> --
> 2.43.0
>
>
On Wed, 18 Feb 2026 16:19:25 +0100, Claudiu <claudiu.beznea@tuxon.dev> said:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add GPIO set_config to allow setting GPIO specific functionalities.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 863e779dda02..641ae1adfd4a 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
> rzg2l_gpio_direction_input(chip, offset);
> }
>
> +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
> + unsigned long config)
> +{
> + switch (pinconf_to_config_param(config)) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> + case PIN_CONFIG_DRIVE_PUSH_PULL:
> + case PIN_CONFIG_SLEW_RATE:
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> + case PIN_CONFIG_POWER_SOURCE:
> + return pinctrl_gpio_set_config(chip, offset, config);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static const char * const rzg2l_gpio_names[] = {
> "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
> "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
> @@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> chip->direction_output = rzg2l_gpio_direction_output;
> chip->get = rzg2l_gpio_get;
> chip->set = rzg2l_gpio_set;
> + chip->set_config = rzg2l_gpio_set_config;
> chip->label = name;
> chip->parent = pctrl->dev;
> chip->owner = THIS_MODULE;
> --
> 2.43.0
>
>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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