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([82.78.167.73]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796a5b2d1sm45366347f8f.4.2026.02.18.07.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 07:19:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, linusw@kernel.org, brgl@kernel.org Cc: claudiu.beznea@tuxon.dev, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH] pinctrl: renesas: rzg2l: Add GPIO set_config Date: Wed, 18 Feb 2026 17:19:25 +0200 Message-ID: <20260218151925.1104098-1-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add GPIO set_config to allow setting GPIO specific functionalities. Signed-off-by: Claudiu Beznea Reviewed-by: Bartosz Golaszewski Reviewed-by: Lad Prabhakar Reviewed-by: Linus Walleij --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..641ae1adfd4a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1848,6 +1848,25 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, = unsigned int offset) rzg2l_gpio_direction_input(chip, offset); } =20 +static int rzg2l_gpio_set_config(struct gpio_chip *chip, unsigned int offs= et, + unsigned long config) +{ + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + case PIN_CONFIG_SLEW_RATE: + case PIN_CONFIG_DRIVE_STRENGTH: + case PIN_CONFIG_DRIVE_STRENGTH_UA: + case PIN_CONFIG_POWER_SOURCE: + return pinctrl_gpio_set_config(chip, offset, config); + default: + return -EOPNOTSUPP; + } +} + static const char * const rzg2l_gpio_names[] =3D { "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", @@ -2819,6 +2838,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *= pctrl) chip->direction_output =3D rzg2l_gpio_direction_output; chip->get =3D rzg2l_gpio_get; chip->set =3D rzg2l_gpio_set; + chip->set_config =3D rzg2l_gpio_set_config; chip->label =3D name; chip->parent =3D pctrl->dev; chip->owner =3D THIS_MODULE; --=20 2.43.0