[v2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

[PATCH v2 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

Aaron Kling via B4 Relay posted 3 patches 1 month, 1 week ago

Diff against v1 v3
Download series mbox

There is a newer version of this series

.../bindings/interconnect/qcom,osm-l3.yaml         |   1 +
arch/arm64/boot/dts/qcom/sm8550.dtsi               | 367 +++++++++++++++++++++
2 files changed, 368 insertions(+)

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[PATCH v2 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

Posted by Aaron Kling via B4 Relay 1 month, 1 week ago

Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Changes in v2:
- Squash first two patches
- Update opp tables in last patch to match how the downstream driver
  parses those tables
- Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com

---
Aaron Kling (3):
      dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
      arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes
      arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths

 .../bindings/interconnect/qcom,osm-l3.yaml         |   1 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi               | 367 +++++++++++++++++++++
 2 files changed, 368 insertions(+)
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207

Best regards,
-- 
Aaron Kling <webgeek1234@gmail.com>