From nobody Sun Apr 5 13:26:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8812130AABC; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; cv=none; b=Z1NoDQSnDbC+GyoBd6UDfOV37RDk4mfz/iXmUOMRxjgQymB3KH43thAzVjaybxRCNJzzOuRJA4Xt86/B+h+IaAALm7J13HGxwjTvwA++1HkrkbRQIZdWyWssPVSPtxOrvfeVK705tjb/ZhVplOIrk16MeAPqOdSWCZNq6bNQWtU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; c=relaxed/simple; bh=a05snlq6Y0wUIyGYFKz6Aof2Ecgn10TWqXHZr/LmJdY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WkhCECHEm253U4BkwtwthYy1fyUvxjGzgvzCE/babTX4zv6v03pnHuBrgf1vdL4eTG3hF7JuD8FIX386rgX2mbOiQtMacJgVnPVcDsDH2T5stroLHF69m9kqJXGdg5pUiXqVORPbFd83BcGnVOYx18T7vuDiyh9nwmXjV6s/pfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HQ8wRE/R; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HQ8wRE/R" Received: by smtp.kernel.org (Postfix) with ESMTPS id 32E9FC19423; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771438581; bh=a05snlq6Y0wUIyGYFKz6Aof2Ecgn10TWqXHZr/LmJdY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HQ8wRE/RY7DBOnZ4s5mPPRQ5bsbEfPXEZZ54USKtr9Rv30O5X91c7Q5SCCrdPAcq3 w0bL5VOnL8uPYQ4OA5taFgWxcAHkPZ4YkI6ztS7vQVoZ50HLXhFVoy597l73l2S+Hb gwgtU97LDPODGPIzME6AtDJGvsEXWsb3RR6u0ptP+kIwkVn9M+tX+XlKEDRR+WxCZC FEga0uSlip/ozYFtcTjFQSRXU/4nJz95ZJCioopaZIAYR6obzCyCF5PCazjo/3KZ0d k3XiKKniy8Hv5yRuQ+bXJBtQpvdh+bGfuSh50M7ooaX/zpK93z6E0nYsRT4kfG1ZSo 2nvrK55j50MyQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D32FE9A047; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 18 Feb 2026 12:16:18 -0600 Subject: [PATCH v2 1/3] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260218-sm8550-ddr-bw-scaling-v2-1-43a2b6d47e70@gmail.com> References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771438580; l=897; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=QL4QtlV1mkUECwvUyM6TwRVGqKLGQYeQGpH9Y7qGjM4=; b=MPZfDr/vlSXG8c8OTZEeBIXBCkRI2FikGcYjpKZttCkgoRZKuTJvHcMR3TxO6VYE541zP1+Sf 1WvZfT1x9X8BYvMHwqTXPxTKA87bD1fieyQE4o0JFog/aEpNqvd2kPK X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Document the OSM L3 found in the Qualcomm SM8550 platform. Signed-off-by: Aaron Kling Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 4b9b98fbe8f22258c209e8337bb4517e5f5888e8..3cbe2c3701f77d5d70082092043= f2b2ccbd64905 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -34,6 +34,7 @@ properties: - qcom,sm6375-cpucp-l3 - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 + - qcom,sm8550-epss-l3 - qcom,sm8650-epss-l3 - const: qcom,epss-l3 - items: --=20 2.52.0 From nobody Sun Apr 5 13:26:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8804B309EEC; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; cv=none; b=iIWbxcEAZX8cigY/M5nimiqWapXY45T8xTt1ypZd8/tPXFGm5y0ArGV4Z9jbqIXboGeZoCt+DZ8K18VADudVCSewfJtX+F8L32YhN24UgUy/lRsZBn624KSl6lb63/jcCA+K7yKsI0YT4g2Z9ctQZYOPursxqBW5/dAFNYUBiSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; c=relaxed/simple; bh=G4D4eRDmZ3zLHtlTCwr9vTCHs+6N4+BLBkJbK4k9c60=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HBCGOuiFos+TCgh/VvxLqMhz/Qy3VbceZ7WP/ShGsvIiDABzDXdp5af5hwhx8MPqud4AktnYpDIpAiFzIYn22wq/diR0L2GogTxttnG8UtjOW06DSVppx7w1OhSNSDFf8/rymNJFCbgFk9DcuKx7kXY2aHTa4+JVQcXlF88XLk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zl3KfNDD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zl3KfNDD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 44957C19422; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771438581; bh=G4D4eRDmZ3zLHtlTCwr9vTCHs+6N4+BLBkJbK4k9c60=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Zl3KfNDDB05MFHoPcXpiHwFUE6yAa3bnGJLRaSnJKVd9/ikGw7tWJ3WpvanB8k12K o3sJ/hvRFymmbE7v1M3ocOGGDHZDoN5WwAL8afVkqTdq163PZ4JHQuRe2h0Fuwenw5 ojnI1hdpswe90xfgwnKqbH5NuwD/i5CQxzu1MC1KxJAKMCjosqtEsoORq59VSvpGhm Io/yVyXu5BOYLv/IsKQKDY+JHZn0HQfIrLWCXww6MptqNCwlwHg1oy7EQye6B3B09g oJTDMKEguLqVGcSNz1tlgJp4PJ6T6GPwt9lNp7GCddjFsqFOrhfO6VEt77lJfdgjrA D/wX3RDb2Jx9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32B28E9A04A; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 18 Feb 2026 12:16:19 -0600 Subject: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com> References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771438580; l=5920; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=nk9umh4fIRgNVJ6t2hcRpym0E82gtFPD4gJGRGEKYHg=; b=NjfB+RLobCH+wF7j8pY/opYwu72NwoTx17WwnloJp7L4GXxbDxuQ3/jsWDJ8hRM7O6du4eJlK I7nhOyjxF/AA1pHCN867VGSvUoYwD3YMVgBzGspthBJT+aF157uxFLc X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OSC L3 Cache controller node. Also add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 59 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..e6cb8bf40f9f8ed6d02db124056= c5814af32fa08 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,12 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_0: l2-cache { compatible =3D "cache"; @@ -104,6 +111,12 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_100: l2-cache { compatible =3D "cache"; @@ -125,6 +138,12 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_200: l2-cache { compatible =3D "cache"; @@ -146,6 +165,12 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_300: l2-cache { compatible =3D "cache"; @@ -167,6 +192,12 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_400: l2-cache { compatible =3D "cache"; @@ -188,6 +219,12 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_500: l2-cache { compatible =3D "cache"; @@ -209,6 +246,12 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_600: l2-cache { compatible =3D "cache"; @@ -230,6 +273,12 @@ cpu7: cpu@700 { qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_700: l2-cache { compatible =3D "cache"; @@ -5437,6 +5486,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,sm8550-epss-l3", "qcom,epss-l3"; + reg =3D <0 0x17d90000 0 0x1000>; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0 0x17d91000 0 0x1000>, --=20 2.52.0 From nobody Sun Apr 5 13:26:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A77230AAC2; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; cv=none; b=AjlbIGh/BLfAkXuNubTBRYtOlEE78YO4JaF4q5/ks6J10js+fXNWPSHYQa11LAfpOFxAC0uh6D1Y5uCsz7lYYVYOUFPx5Y87Omk7Zh+IzXBrr/149UYGDWL8Bsux78ZMw2BR/A0EGrQjSa2uVyQFYz5OxL/wxZHGgNHUMPvOsd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771438581; c=relaxed/simple; bh=BLKB5b21EKa+KPyw6tXgpvna7Bnyp9CtiG3oiOy47GE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qFTHVDLCqxMWeAn2wd+84A/0DLhLSQ7vEi5gvpFMmnHlZeDXT5slf3ZtJvB6L3sMHTlTUUpZ61d9YHdw6VjF4ErPBKTaux+4cilEqCKL8/iCKXNdiOP/ppwiYYuA3EZNInp8LGn0TSCdds0XOrxbnf/0LIa4G+NYfSCW3CxF8C0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UeEBKsJK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UeEBKsJK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 556EAC19425; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771438581; bh=BLKB5b21EKa+KPyw6tXgpvna7Bnyp9CtiG3oiOy47GE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UeEBKsJKDEy4ULpdeoDkEGpPpzcpLgZc65P/gsod+BFmY1+oSHTyNcl3KMB0SKn8b 4VeOm9Fj+1rdfvVZBbKvFcH/jMIruoAftE034RsqKNDN89QY6pRx/mIBu7imVOZfvI lC52lsPRMaZKLI5H+uYAdZcZPMF+C35T2XzuKr7KFSTqJhrG+QHDbsjSbtOfL4/5ZL msPlW5WztDs6awcAP5viEXMb/WWvClODUdT10i2YVoxtvSMjHgEHo66YNG3+65mDnf OKAJyp7kYv9WakMTVwdNxeh3y0Xkgk4O5xAB5jkT1k9ssT4V2m5XKxHD8Twz93otMP sdOpeQMG1xQTg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 472EAE9A02C; Wed, 18 Feb 2026 18:16:21 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Wed, 18 Feb 2026 12:16:20 -0600 Subject: [PATCH v2 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260218-sm8550-ddr-bw-scaling-v2-3-43a2b6d47e70@gmail.com> References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> In-Reply-To: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771438580; l=12245; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=85HscMMOyXUPnbY+5BZN+EPpT/ZXYecdKO3kDfW5w1o=; b=HolGef5kdVqtWB/NY4ohDeuOoHBvhbBfNINyMuLp8mAW/rF5Iq/Br8FsqeTrJtFK2kKxhmC48 3ZIwxMNVQIyDdIDTTNQcDxg0zvk6PXSdpPnnqk4bSVj598ucme+o3Yo X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running a QCS8550 device. Signed-off-by: Aaron Kling Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 308 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 308 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e6cb8bf40f9f8ed6d02db124056c5814af32fa08..de4d43f7b8d2416997db70c98b0= fc36d25f3c2a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -79,6 +79,7 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -111,6 +112,7 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -138,6 +140,7 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -165,6 +168,7 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -192,6 +196,7 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -219,6 +224,7 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -246,6 +252,7 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -273,6 +280,7 @@ cpu7: cpu@700 { qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; + operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -446,6 +454,306 @@ memory@a0000000 { reg =3D <0 0xa0000000 0 0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-441600000 { + opp-hz =3D /bits/ 64 <441600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz =3D /bits/ 64 <556800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz =3D /bits/ 64 <672000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1056000 * 32)>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1152000 * 32)>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (1267200 * 32)>; + }; + + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1689600 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz =3D /bits/ 64 <844800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2054400000 { + opp-hz =3D /bits/ 64 <2054400000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2323200000 { + opp-hz =3D /bits/ 64 <2323200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + opp-peak-kBps =3D <(933000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2803200000 { + opp-hz =3D /bits/ 64 <2803200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-864000000 { + opp-hz =3D /bits/ 64 <864000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1132800000 { + opp-hz =3D /bits/ 64 <1132800000>; + opp-peak-kBps =3D <(300000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1478400000 { + opp-hz =3D /bits/ 64 <1478400000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1843200000 { + opp-hz =3D /bits/ 64 <1843200000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1267200 * 32)>; + }; + + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-2092800000 { + opp-hz =3D /bits/ 64 <2092800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2227200000 { + opp-hz =3D /bits/ 64 <2227200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2342400000 { + opp-hz =3D /bits/ 64 <2342400000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2476800000 { + opp-hz =3D /bits/ 64 <2476800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2726400000 { + opp-hz =3D /bits/ 64 <2726400000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2841600000 { + opp-hz =3D /bits/ 64 <2841600000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2956800000 { + opp-hz =3D /bits/ 64 <2956800000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-3187200000 { + opp-hz =3D /bits/ 64 <3187200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + }; + pmu-a510 { compatible =3D "arm,cortex-a510-pmu"; interrupts =3D ; --=20 2.52.0