drivers/misc/pci_endpoint_test.c | 34 ++++++++++++++++++++++++--- drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++--------- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 +++---- drivers/pci/endpoint/pci-epc-core.c | 5 ++-- include/linux/pci-epc.h | 13 ++++++++-- 5 files changed, 64 insertions(+), 22 deletions(-)
When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
EPF does not allocate backing memory. The host-side pci_endpoint_test driver
still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
longer available for real use (e.g. host DMA via BAR4).
This series addresses that by:
1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
for unused BARs that the EPC must disable in .init() and the EPF must not
use. pci_epc_get_next_free_bar() treats both as not free.
2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
enabled so the host can use MSI-X and DMA.
3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
(test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
to the pci_endpoint_test_tbl so the host driver can bind and run tests
without corrupting MSI-X or DMA registers.
4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
(BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
64-bit BAR0 and BAR2.
With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.
pci_endpoint_test results on Tegra234 SoC,
$ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma
TAP version 13
1..13
Starting 13 tests from 8 test cases.
RUN pci_ep_bar.BAR0.BAR_TEST ...
OK pci_ep_bar.BAR0.BAR_TEST
ok 1 pci_ep_bar.BAR0.BAR_TEST
RUN pci_ep_bar.BAR1.BAR_TEST ...
OK pci_ep_bar.BAR1.BAR_TEST
ok 2 pci_ep_bar.BAR1.BAR_TEST
RUN pci_ep_bar.BAR2.BAR_TEST ...
OK pci_ep_bar.BAR2.BAR_TEST
ok 3 pci_ep_bar.BAR2.BAR_TEST
RUN pci_ep_bar.BAR3.BAR_TEST ...
OK pci_ep_bar.BAR3.BAR_TEST
ok 4 pci_ep_bar.BAR3.BAR_TEST
RUN pci_ep_bar.BAR4.BAR_TEST ...
OK pci_ep_bar.BAR4.BAR_TEST
ok 5 pci_ep_bar.BAR4.BAR_TEST
RUN pci_ep_bar.BAR5.BAR_TEST ...
OK pci_ep_bar.BAR5.BAR_TEST
ok 6 pci_ep_bar.BAR5.BAR_TEST
RUN pci_ep_basic.CONSECUTIVE_BAR_TEST ...
OK pci_ep_basic.CONSECUTIVE_BAR_TEST
ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST
RUN pci_ep_basic.LEGACY_IRQ_TEST ...
OK pci_ep_basic.LEGACY_IRQ_TEST
ok 8 pci_ep_basic.LEGACY_IRQ_TEST
RUN pci_ep_basic.MSI_TEST ...
SKIP MSI17 is disabled
OK pci_ep_basic.MSI_TEST
ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled
RUN pci_ep_basic.MSIX_TEST ...
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7
pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8
SKIP MSI-X9 is disabled
OK pci_ep_basic.MSIX_TEST
ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled
RUN pci_ep_data_transfer.memcpy.READ_TEST ...
OK pci_ep_data_transfer.memcpy.READ_TEST
ok 11 pci_ep_data_transfer.memcpy.READ_TEST
RUN pci_ep_data_transfer.memcpy.WRITE_TEST ...
OK pci_ep_data_transfer.memcpy.WRITE_TEST
ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST
RUN pci_ep_data_transfer.memcpy.COPY_TEST ...
OK pci_ep_data_transfer.memcpy.COPY_TEST
ok 13 pci_ep_data_transfer.memcpy.COPY_TEST
PASSED: 13 / 13 tests passed.
2 skipped test(s) detected. Consider enabling relevant config options to improve coverage.
Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Manikanta Maddireddy (4):
PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics
PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode
misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs
PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5
drivers/misc/pci_endpoint_test.c | 34 ++++++++++++++++++++++++---
drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++---------
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 +++----
drivers/pci/endpoint/pci-epc-core.c | 5 ++--
include/linux/pci-epc.h | 13 ++++++++--
5 files changed, 64 insertions(+), 22 deletions(-)
---
base-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62
change-id: 20260217-master-27db95eb02bd
Best regards,
--
Manikanta Maddireddy <mmaddireddy@nvidia.com>
On Tue, Feb 17, 2026 at 11:24:40AM +0530, Manikanta Maddireddy wrote: > When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the > EPF does not allocate backing memory. The host-side pci_endpoint_test driver > still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to > BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks > CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only > BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no > longer available for real use (e.g. host DMA via BAR4). > > This series addresses that by: > > 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core. > BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may > leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is > for unused BARs that the EPC must disable in .init() and the EPF must not > use. pci_epc_get_next_free_bar() treats both as not free. > > 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4: > BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA. > Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay > enabled so the host can use MSI-X and DMA. > > 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the > destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5 > (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B) > to the pci_endpoint_test_tbl so the host driver can bind and run tests > without corrupting MSI-X or DMA registers. > > 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint > (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of > 64-bit BAR0 and BAR2. > > With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit > BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use. > Hello Manikanta, There are quite a few things that I think we should implement differently, please see: https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u I'm not trying to take credit from you, for all I care, feel free to take over the series and add you Co-developed-by on all the patches. I just though that it would be easier to explain with code rather than a lot of back and forth. Hopefully we can send a V2 that includes more detailed BAR_RESERVED descriptions, that includes what are behind each BAR_RESERVED (including sizes of each backing MSI-X table/ATU regs/eDMA regs/whatever) in pcie-tegra194.c. I also have a Nvidia Jetson Orin Nano board that I can run in EP mode, so hopefully we can collaborate to get something merged for v7.1. Kind regards, Niklas
On 18/02/26 3:08 am, Niklas Cassel wrote: > On Tue, Feb 17, 2026 at 11:24:40AM +0530, Manikanta Maddireddy wrote: >> When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the >> EPF does not allocate backing memory. The host-side pci_endpoint_test driver >> still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to >> BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks >> CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only >> BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no >> longer available for real use (e.g. host DMA via BAR4). >> >> This series addresses that by: >> >> 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core. >> BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may >> leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is >> for unused BARs that the EPC must disable in .init() and the EPF must not >> use. pci_epc_get_next_free_bar() treats both as not free. >> >> 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4: >> BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA. >> Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay >> enabled so the host can use MSI-X and DMA. >> >> 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the >> destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5 >> (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B) >> to the pci_endpoint_test_tbl so the host driver can bind and run tests >> without corrupting MSI-X or DMA registers. >> >> 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint >> (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of >> 64-bit BAR0 and BAR2. >> >> With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit >> BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use. >> > Hello Manikanta, > > There are quite a few things that I think we should implement differently, > please see: > https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u > > I'm not trying to take credit from you, for all I care, feel free to take > over the series and add you Co-developed-by on all the patches. > > I just though that it would be easier to explain with code rather than a > lot of back and forth. > > Hopefully we can send a V2 that includes more detailed BAR_RESERVED > descriptions, that includes what are behind each BAR_RESERVED (including > sizes of each backing MSI-X table/ATU regs/eDMA regs/whatever) in > pcie-tegra194.c. > > I also have a Nvidia Jetson Orin Nano board that I can run in EP mode, > so hopefully we can collaborate to get something merged for v7.1. > > > Kind regards, > Niklas Hi Niklas, I marked my series "Handled Elsewhere". I sent new series to define HW reserved BARs. https://lore.kernel.org/linux-pci/20260222193456.2460963-1-mmaddireddy@nvidia.com/T/#t Thanks, Manikanta
Apologies for sending the email twice. The mailing lists in CC were missing in the first email. I’ve added them and resent it. Thanks, Manikanta On 17/02/26 11:24 am, Manikanta Maddireddy wrote: > When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the > EPF does not allocate backing memory. The host-side pci_endpoint_test driver > still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to > BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks > CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only > BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no > longer available for real use (e.g. host DMA via BAR4). > > This series addresses that by: > > 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core. > BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may > leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is > for unused BARs that the EPC must disable in .init() and the EPF must not > use. pci_epc_get_next_free_bar() treats both as not free. > > 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4: > BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA. > Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay > enabled so the host can use MSI-X and DMA. > > 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the > destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5 > (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B) > to the pci_endpoint_test_tbl so the host driver can bind and run tests > without corrupting MSI-X or DMA registers. > > 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint > (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of > 64-bit BAR0 and BAR2. > > With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit > BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use. > > pci_endpoint_test results on Tegra234 SoC, > > $ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma > TAP version 13 > 1..13 > Starting 13 tests from 8 test cases. > RUN pci_ep_bar.BAR0.BAR_TEST ... > OK pci_ep_bar.BAR0.BAR_TEST > ok 1 pci_ep_bar.BAR0.BAR_TEST > RUN pci_ep_bar.BAR1.BAR_TEST ... > OK pci_ep_bar.BAR1.BAR_TEST > ok 2 pci_ep_bar.BAR1.BAR_TEST > RUN pci_ep_bar.BAR2.BAR_TEST ... > OK pci_ep_bar.BAR2.BAR_TEST > ok 3 pci_ep_bar.BAR2.BAR_TEST > RUN pci_ep_bar.BAR3.BAR_TEST ... > OK pci_ep_bar.BAR3.BAR_TEST > ok 4 pci_ep_bar.BAR3.BAR_TEST > RUN pci_ep_bar.BAR4.BAR_TEST ... > OK pci_ep_bar.BAR4.BAR_TEST > ok 5 pci_ep_bar.BAR4.BAR_TEST > RUN pci_ep_bar.BAR5.BAR_TEST ... > OK pci_ep_bar.BAR5.BAR_TEST > ok 6 pci_ep_bar.BAR5.BAR_TEST > RUN pci_ep_basic.CONSECUTIVE_BAR_TEST ... > OK pci_ep_basic.CONSECUTIVE_BAR_TEST > ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST > RUN pci_ep_basic.LEGACY_IRQ_TEST ... > OK pci_ep_basic.LEGACY_IRQ_TEST > ok 8 pci_ep_basic.LEGACY_IRQ_TEST > RUN pci_ep_basic.MSI_TEST ... > SKIP MSI17 is disabled > OK pci_ep_basic.MSI_TEST > ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled > RUN pci_ep_basic.MSIX_TEST ... > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7 > pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5) > pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8 > SKIP MSI-X9 is disabled > OK pci_ep_basic.MSIX_TEST > ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled > RUN pci_ep_data_transfer.memcpy.READ_TEST ... > OK pci_ep_data_transfer.memcpy.READ_TEST > ok 11 pci_ep_data_transfer.memcpy.READ_TEST > RUN pci_ep_data_transfer.memcpy.WRITE_TEST ... > OK pci_ep_data_transfer.memcpy.WRITE_TEST > ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST > RUN pci_ep_data_transfer.memcpy.COPY_TEST ... > OK pci_ep_data_transfer.memcpy.COPY_TEST > ok 13 pci_ep_data_transfer.memcpy.COPY_TEST > PASSED: 13 / 13 tests passed. > 2 skipped test(s) detected. Consider enabling relevant config options to improve coverage. > Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0 > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> > --- > Manikanta Maddireddy (4): > PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics > PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode > misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs > PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5 > > drivers/misc/pci_endpoint_test.c | 34 ++++++++++++++++++++++++--- > drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++--------- > drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 +++---- > drivers/pci/endpoint/pci-epc-core.c | 5 ++-- > include/linux/pci-epc.h | 13 ++++++++-- > 5 files changed, 64 insertions(+), 22 deletions(-) > --- > base-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62 > change-id: 20260217-master-27db95eb02bd > > Best regards,
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