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Document BAR_RESERVED for two uses: (1) HW-backed BARs (e.g. MSI-X table, DMA regs) that the EPC may leave enabled for the host, and (2) the second register of a 64-bit BAR (high 32 bits) when the preceding BAR has only_64bit set. Update pci_epc_get_next_free_bar() to treat both BAR_RESERVED and BAR_DISABLED as not free so EPF drivers do not allocate or use these BARs. This allows EPC drivers such as Tegra194 to keep HW-backed 64-bit BARs (MSI-X, DMA) enabled while still preventing EPF from using reserved or disabled BARs. Signed-off-by: Manikanta Maddireddy --- drivers/pci/endpoint/pci-epc-core.c | 5 +++-- include/linux/pci-epc.h | 13 +++++++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index ca7f19cc973a..1d6b04ac4fc5 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -103,8 +103,9 @@ enum pci_barno pci_epc_get_next_free_bar(const struct p= ci_epc_features bar++; =20 for (i =3D bar; i < PCI_STD_NUM_BARS; i++) { - /* If the BAR is not reserved, return it. */ - if (epc_features->bar[i].type !=3D BAR_RESERVED) + /* If the BAR is not reserved or disabled, return it. */ + if (epc_features->bar[i].type !=3D BAR_RESERVED && + epc_features->bar[i].type !=3D BAR_DISABLED) return i; } =20 diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 4286bfdbfdfa..9b3714a0dafc 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -191,13 +191,21 @@ struct pci_epc { * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability. * NOTE: An EPC driver can currently only set a single supported * size. - * @BAR_RESERVED: The BAR should not be touched by an EPF driver. + * @BAR_RESERVED: The BAR should not be touched by an EPF driver. Used for: + * (1) HW-backed BARs (e.g. MSI-X table, DMA regs) that the EPC + * may leave enabled for the host; (2) the second register + * of a 64-bit BAR (the high 32 bits), when the preceding + * BAR has only_64bit set. + * @BAR_DISABLED: The BAR is unused; the EPC must disable it in .init(); t= he + * EPF must not use it; it is not returned by + * pci_epc_get_next_free_bar(). */ enum pci_epc_bar_type { BAR_PROGRAMMABLE =3D 0, BAR_FIXED, BAR_RESIZABLE, BAR_RESERVED, + BAR_DISABLED, }; =20 /** @@ -212,7 +220,8 @@ enum pci_epc_bar_type { * only_64bit should not be set on a BAR of type BAR_RESERVED. * (If BARx is a 64-bit BAR that an EPF driver is not allowed to * touch, then both BARx and BARx+1 must be set to type - * BAR_RESERVED.) + * BAR_RESERVED. BAR_RESERVED is used both for HW-backed BARs and + * for the high half of a 64-bit BAR.) */ struct pci_epc_bar_desc { enum pci_epc_bar_type type; --=20 2.34.1 From nobody Fri Apr 3 02:56:59 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012066.outbound.protection.outlook.com [52.101.53.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 789EA1FC7C5; Tue, 17 Feb 2026 05:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771307755; cv=fail; b=MymMIl/7araAmhxugJxKbztLzJzUnUvxKegydS1a3pSDCa521PeOZ5NwAy0h9Da18IPAPj0p1QUKBmzaMrwl6bUcqXtBHPzO3EYwteWMXk7rkWApb6aObrZZ0o9nywjt2yKZ9i3TVdcGjSAz9AUijMfNl4rqzXbb04S2EyJGycw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771307755; c=relaxed/simple; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: v+lUwcvDySUQLGetDuI3v4dEW+SLGOwvmtb4FJxvKLwKP+pK8Bca4r9ZI3eiHOfrEXajf9SObYXg9cK1j9WNH86vRnBIamtMPAqh+dOKyqjqGFaMomcTdl4dFZoQzFMbGBUHBOlK2d3Yy23g8OvtPgTzD2Jww7HDA78JUJB5+UbwJ2RPjJEDd+wgB1RZtd8aDx1G/gf5Hu/Ei2BzSdgiPJlLEyOV318WY5fk8s0mgOlKia1clLGGzORimUy5ZRYk2KLvhLR7uAUFofQJkCmXimVSPNZIXpc4LLi6otGXdrDobBNcY30dXL9Z40AWK9IfI8njVUkT8zUb0c1cFuHw1s7rIvEU8urS9QNXJAd3HbA8gnTTQOSGWbl4V2zsIYR3c85HouXZ47McPDpOjSr/OfiY9FMzlEb4HbtIPvAw/cJ29YXtX5Oz7uJPsw4Fljcl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2026 05:55:45.8780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 422cd343-aefc-4093-8df3-08de6de9319c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4292 Tegra194 endpoint exposes three 64-bit BARs at indices 0, 2, and 4: - BAR0+BAR1: EPF test/data (first 64-bit BAR) - BAR2+BAR3: MSI-X table (HW-backed) - BAR4+BAR5: DMA registers (HW-backed) Update tegra_pcie_epc_features so that BAR0 is BAR_FIXED with only_64bit, BAR1 is BAR_RESERVED (high half of 64-bit BAR0), BAR2/BAR3 are BAR_RESERVED with only_64bit on BAR2 (MSI-X), and BAR4/BAR5 are BAR_RESERVED with only_64bit on BAR4 (DMA). In tegra_pcie_ep_init(), reset only BAR0 and BAR1 so that the first 64-bit BAR is disabled until the EPF enables it via set_bar. Do not reset BAR2+BAR3 or BAR4+BAR5 so that MSI-X and DMA remain enabled for the host. This keeps CONSECUTIVE_BAR_TEST and DMA tests working while allowing the host to use 64-bit BAR 2 (MSI-X) and 64-bit BAR 4 (DMA) for real use. BAR0 is capabale of supporting various sizes using DBI2 BAR registers which are programmed in dw_pcie_ep_set_bar_programmable(), remove 1 MB size limit from pci_epc_features. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 1b4fc6a9bed1..6734d1336ef1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1948,11 +1948,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int ir= q, void *arg) static void tegra_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); - enum pci_barno bar; =20 - for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) - dw_pcie_ep_reset_bar(pci, bar); -}; + /* + * Only reset the first 64-bit BAR (BAR0+BAR1); EPF will enable it via se= t_bar. + * BAR2+BAR3 (MSI-X table) and BAR4+BAR5 (DMA regs) are HW-backed and must + * stay enabled. + */ + dw_pcie_ep_reset_bar(pci, BAR_0); + dw_pcie_ep_reset_bar(pci, BAR_1); +} =20 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 ir= q) { @@ -2009,16 +2013,16 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_e= p *ep, u8 func_no, return 0; } =20 +/* Tegra194 EP: BAR0 =3D programmable BAR, BAR2 =3D MSI-X table, BAR4 =3D = DMA regs. */ static const struct pci_epc_features tegra_pcie_epc_features =3D { .linkup_notifier =3D true, .msi_capable =3D true, - .bar[BAR_0] =3D { .type =3D BAR_FIXED, .fixed_size =3D SZ_1M, - .only_64bit =3D true, }, - .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_2] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_4] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_0] =3D { .type =3D BAR_PROGRAMMABLE, .only_64bit =3D true, }, + .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, /* high half of 64-bit BAR0 = */ + .bar[BAR_2] =3D { .type =3D BAR_RESERVED, .only_64bit =3D true, }, /* MSI= -X table */ + .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, /* high half of 64-bit BAR2 = */ + .bar[BAR_4] =3D { .type =3D BAR_RESERVED, .only_64bit =3D true, }, /* DMA= regs */ + .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, /* high half of 64-bit BAR4 = */ .align =3D SZ_64K, }; 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Mon, 16 Feb 2026 21:55:24 -0800 From: Manikanta Maddireddy To: Niklas Cassel , Vidya Sagar , Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , "Kishon Vijay Abraham I" , Bjorn Helgaas , "Lorenzo Pieralisi" , Rob Herring , "Thierry Reding" , Jonathan Hunter , Arnd Bergmann , Greg Kroah-Hartman , Kunihiko Hayashi , Masami Hiramatsu CC: Manikanta Maddireddy , , , , Subject: [PATCH 3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs Date: Tue, 17 Feb 2026 11:24:43 +0530 Message-ID: <20260217-master-v1-3-727e26cdfaf5@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260217-master-v1-0-727e26cdfaf5@nvidia.com> References: <20260217-master-v1-0-727e26cdfaf5@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.3 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A345:EE_|IA4PR12MB9785:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f6967b6-6d0b-4d34-9f57-08de6de92efd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014|921020; 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When a BAR is skipped, it is not written or read in the consecutive BAR test, and PCITEST_BAR ioctl for that BAR returns -EINVAL. Add Tegra endpoint test data with bar_skip_mask set to skip BAR1 through BAR5 (test only BAR0, the first 64-bit BAR). Add pci_endpoint_test_tbl entries for NVIDIA Tegra194 EP (device ID 0x1AD4) and Tegra234 EP (device ID 0x229B) so the host test driver can bind and run tests without corrupting MSI-X or DMA registers. Signed-off-by: Manikanta Maddireddy --- drivers/misc/pci_endpoint_test.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_t= est.c index 1c0fd185114f..4c9f02dbc41b 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -100,6 +100,12 @@ =20 #define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588 =20 +#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP 0x1ad4 +#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP 0x229b + +/* BARs 1-5 are HW-backed (MSI-X, DMA) or high half of 64-bit BAR0; skip B= AR test */ +#define TEGRA_EP_BAR_SKIP_MASK (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5)) + static DEFINE_IDA(pci_endpoint_test_ida); =20 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_te= st, \ @@ -130,11 +136,15 @@ struct pci_endpoint_test { size_t alignment; u32 ep_caps; const char *name; + /* Bitmask of BARs to skip in BAR test (bit N set =3D skip BAR N) */ + u8 bar_skip_mask; }; =20 struct pci_endpoint_test_data { enum pci_barno test_reg_bar; size_t alignment; + /* Bitmask of BARs to skip in BAR test (bit N set =3D skip BAR N) */ + u8 bar_skip_mask; }; =20 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, @@ -393,9 +403,10 @@ static int pci_endpoint_test_bars(struct pci_endpoint_= test *test) int ret; =20 /* Write all BARs in order (without reading). */ - for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) - if (test->bar[bar]) + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar))) pci_endpoint_test_bars_write_bar(test, bar); + } =20 /* * Read all BARs in order (without writing). @@ -404,7 +415,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_t= est *test) * (Reading back the BAR directly after writing can not detect this.) */ for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { - if (test->bar[bar]) { + if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar))) { ret =3D pci_endpoint_test_bars_read_bar(test, bar); if (ret) return ret; @@ -941,6 +952,10 @@ static long pci_endpoint_test_ioctl(struct file *file,= unsigned int cmd, goto ret; if (is_am654_pci_dev(pdev) && bar =3D=3D BAR_0) goto ret; + if (test->bar_skip_mask & (1 << bar)) { + ret =3D 0; + goto ret; + } ret =3D pci_endpoint_test_bar(test, bar); break; case PCITEST_BARS: @@ -1028,6 +1043,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pd= ev, test_reg_bar =3D data->test_reg_bar; test->test_reg_bar =3D test_reg_bar; test->alignment =3D data->alignment; + test->bar_skip_mask =3D data->bar_skip_mask; } =20 init_completion(&test->irq_raised); @@ -1173,6 +1189,12 @@ static const struct pci_endpoint_test_data rk3588_da= ta =3D { .alignment =3D SZ_64K, }; =20 +static const struct pci_endpoint_test_data tegra_ep_data =3D { + .test_reg_bar =3D BAR_0, + .alignment =3D SZ_64K, + .bar_skip_mask =3D TEGRA_EP_BAR_SKIP_MASK, +}; + /* * If the controller's Vendor/Device ID are programmable, you may be able = to * use one of the existing entries for testing instead of adding a new one. @@ -1217,6 +1239,12 @@ static const struct pci_device_id pci_endpoint_test_= tbl[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588), .driver_data =3D (kernel_ulong_t)&rk3588_data, }, + { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP), + .driver_data =3D (kernel_ulong_t)&tegra_ep_data, + }, + { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP), + .driver_data =3D (kernel_ulong_t)&tegra_ep_data, + }, { } }; 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they are unused. Convert them from BAR_RESERVED to BAR_DISABLED. Add comments for BAR_1 and BAR_3 to clarify they are the high halves of 64-bit BAR0 and BAR2. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/co= ntroller/dwc/pcie-uniphier-ep.c index d6e73811216e..cf5131eec7bf 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -425,11 +425,11 @@ static const struct uniphier_pcie_ep_soc_data uniphie= r_pro5_data =3D { .msix_capable =3D false, .align =3D 1 << 16, .bar[BAR_0] =3D { .only_64bit =3D true, }, - .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, /* high half of 64-bit BAR0= */ .bar[BAR_2] =3D { .only_64bit =3D true, }, - .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_4] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, /* high half of 64-bit BAR2= */ + .bar[BAR_4] =3D { .type =3D BAR_DISABLED, }, /* unused */ + .bar[BAR_5] =3D { .type =3D BAR_DISABLED, }, /* unused */ }, }; =20 --=20 2.34.1